EP3C25U256I7 Altera, EP3C25U256I7 Datasheet - Page 56

IC CYCLONE III FPGA 25K 256 UBGA

EP3C25U256I7

Manufacturer Part Number
EP3C25U256I7
Description
IC CYCLONE III FPGA 25K 256 UBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C25U256I7

Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
156
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-UBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
156
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
UFBGA
For Use With
544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C25U256I7
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP3C25U256I7N
Manufacturer:
ALTERA
Quantity:
220
Part Number:
EP3C25U256I7N
Manufacturer:
Altera
Quantity:
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Part Number:
EP3C25U256I7N
Manufacturer:
ALTERA
0
2–12
Table 2–16. Cyclone III LS Devices Differential SSTL I/O Standard Specifications
Table 2–17. Cyclone III LS Devices Differential HSTL I/O Standard Specifications
Table 2–18. Differential I/O Standard Specifications
Cyclone III Device Handbook, Volume 2
SSTL-2
Class I, II
SSTL-18
Class I, II
HSTL-18
Class I, II
HSTL-15
Class I, II
HSTL-12
Class I, II
LVPECL
(Row
I/Os)
LVPECL
(Column
I/Os)
LVDS
(Row
I/Os)
LVDS
(Column
I/Os)
I/O Standard
I/O Standard
Standard
I/O
(3)
(3)
2.375
2.375
2.375
2.375
f
Min
2.375
1.425
Min
1.71
1.14
Min
1.7
V
C CIO
Typ
2.5
2.5
2.5
2.5
V
V
For more information about receiver input and transmitter output waveforms, and for
other differential I/O standards, refer to the
Cyclone III Devices
C CIO
C CIO
Typ
2.5
1.8
(V)
Typ
1.8
1.5
1.2
(V)
(V)
2.625
2.625
2.625
2.625
Max
2.625 0.36
1.575
1.90
Max
Max
1.89
1.26
Min Max Min
100
100
100
100
V
0.25
Min
0.16
Min
V
0.2
0.2
ID
Sw ing(DC )
V
(mV)
DIF(D C)
chapter.
Max
V
V
Max
(V)
V
(V)
C CIO
C CIO
C CIO
0.5
0.5
0.5
0.5
0
1
0
1
0
1
0
1
V
(Note 1)
0.48 * V
CC IO
V
0.175
D
500 Mbps ≤ D
D
D
500 Mbps ≤ D
D
D
500 Mbps ≤ D
D
D
500 Mbps ≤ D
D
CC IO
700 Mbps
700 Mbps
700 Mbps
700 Mbps
Min
/2 – 0.2
0.85
0.71
Min
M AX
M AX
M AX
M AX
M AX
M AX
M AX
M AX
/2 –
> 700 Mbps
> 700 Mbps
Condition
≤ 500 Mbps
≤ 500 Mbps
≤ 500 Mbps
> 700 Mbps
≤ 500 Mbps
> 700 Mbps
CC IO
(Part 1 of 2)
V
V
V
ICM
X (A C)
X (A C)
(V)
Typ
Typ
(V)
(V)
MA X
MA X
MA X
MA X
V
V
0.52 *
0.175
C CIO
C CIO
Max
Max
0.95
0.79
V
0.2
High-Speed Differential Interfaces in
CC IO
/2 +
/2 +
Max Min Typ Max
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.85
1.6
1.6
1.6
1.6
Min Max
V
0.7
0.5
0.48 *
247
247
Sw ing(AC )
0.85
0.71
Min
V
Chapter 2: Cyclone III LS Device Data Sheet
C CIO
V
O D
V
V
(mV)
(V)
CC IO
CC IO
V
© December 2009 Altera Corporation
C M(D C)
Typ
(2)
(V)
600
600
V
V
0.125
0.125
CC IO
CC IO
Min
0.52 *
Max
0.95
0.79
/2 –
/2 –
V
CC IO
1.125 1.25 1.375
1.125 1.25 1.35
Electrical Characteristics
Min
V
O X(AC )
Typ
V
Min
OS
0.4
0.4
0.3
(V)
Typ
(V)
V
DIF(AC )
V
V
(2)
0.125
0.125
CC IO
CC IO
Max
0.48 *
Max
(V)
V
Max
/2 +
/2 +
CC IO

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