EP3C25U256I7 Altera, EP3C25U256I7 Datasheet - Page 38

• Manufacturer Part Number: EP3C25U256I7
• Description: IC CYCLONE III FPGA 25K 256 UBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25U256I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 156
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-UBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 156
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: UFBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

1–28
Table 1–39. Glossary (Part 2 of 5)
Cyclone III Device Handbook, Volume 2
Letter
M
N
O
Q
K
L
P
J
JTAG Waveform
PLL Block
Term
—
—
—
—
—
—
Captured
The following block diagram highlights the PLL Specification parameters.
Core Clock
Driven
Signal
Signal
to be
to be
Key
TMS
CLK
TDO
TCK
TDI
Reconfigurable in User Mode
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
Switchover
f
IN
t
JSH
N
t
t
JPCO
JSCO
t
t
f
INPFD
JPSU_TDI
JPSU_TMS
Definitions
PFD
—
—
—
—
—
—
M
CP
t
JSXZ
t
JPH
Phase tap
LF
Chapter 1: Cyclone III Device Data Sheet
VCO
© January 2010 Altera Corporation
t
JPXZ
f
VCO
Counters
C0..C4
CLKOUT Pins
f
f
OUT _EXT
OUT
Glossary
GCLK