EP3C25U256I7 Altera, EP3C25U256I7 Datasheet - Page 65

• Manufacturer Part Number: EP3C25U256I7
• Description: IC CYCLONE III FPGA 25K 256 UBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25U256I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 156
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-UBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 156
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: UFBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
© December 2009
Altera Corporation
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter Timing
Specifications
Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications
f
frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) Emulated LVDS with three-resistor network transmitter is supported at the output pin of all I/O banks.
(2) t
(Part 1 of 2) (Preliminary)
f
frequency)
HSIODR
SW
HSC LK
DUTY
LOCK
HSC LK
(2)
LOC K
Symbol
Symbol
(input clock
(input clock
Table
is the time required for the PLL to lock from the end of device configuration.
2–30:
(Note 1)
Modes
Modes
(Preliminary)
×10
×10
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
C7 and I7
C7 and I7
402.5
402.5
402.5
402.5
Max
Max
370
370
370
370
370
740
740
740
740
740
400
320
320
320
320
320
640
640
640
640
640
200
500
55
1
Cyclone III Device Handbook, Volume 2
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
(Note 1)
C8
C8
402.5
402.5
402.5
402.5
Max
Max
320
320
320
320
320
640
640
640
640
640
400
275
275
275
275
275
550
550
550
550
550
200
550
55
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
MHz
MHz
MHz
MHz
MHz
MHz
ms
ps
ps
%
%
2–21