KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 17

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 3
5.2.2
Table 9
Figure
Specifications.”
Freescale Semiconductor
At recommended operating conditions. See
Internal PLL relock time
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
2. Assumes lightly-loaded, single-processor system; see
3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.
4. Timing is guaranteed by design and characterization.
5. Guaranteed by design.
6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.
7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4]
settings.
lock after a stable V
the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Characteristic
5. Timing specifications for the L3 bus are provided in
provides the processor bus AC timing specifications for the MPC7457 as defined in
provides the SYSCLK input timing diagram.
SYSCLK
Processor Bus AC Specifications
DD
and SYSCLK are reached during the power-on reset sequence. This specification also applies when
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Table 8. Clock AC Timing Specifications (continued)
Symbol
VM
t
Table
KHKL
Figure 3. SYSCLK Input Timing Diagram
t
SYSCLK
4.
Min
—
867 MHz
VM = Midpoint Voltage (OV
VM
Max
100
Maximum Processor Core Frequency
Section 5.2.1, “Clock AC
Min
—
1000 MHz
VM
CV
Max
100
IL
DD
Section 5.2.3, “L3 Clock AC
/2)
Min
CV
1200 MHz
—
t
KR
IH
Specifications” for more information.
Max
100
Electrical and Thermal Characteristics
Min
1267 MHz
—
Max
100
t
KF
Figure 4
Unit
μs
Notes
7
and
17