KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 29

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 10
5.2.4.3
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in
Figure
to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed
L3_CLKn signal it received. The MPC7457 needs a copy of that delayed clock which launched the SRAM
read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and
L3_ECHO_CLK3 must be routed halfway to the SRAMs and returned to the MPC7457 inputs
L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2
are phase-aligned with the input clock received at the SRAMs. The MPC7457 will latch the incoming data
on the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 14
assuming the timing relationships of
Freescale Semiconductor
L3_ECHO_CLK[0,1,2,3]
11. These SRAMs are synchronous to the MPC7457; one L3_CLKn signal is output to each SRAM
Outputs
Note: t
Inputs
Note: t
provides the L3 bus interface AC timing specifications for the configuration shown in
ADDR, L3CNTL
L3DATA WRITE
L3 Data and Data
shows the L3 bus timing diagrams for the MPC7457 interfaced to MSUG2 SRAMs.
L3_CLK[0,1]
time before the clock edge.
time after the clock edge.
L3 Bus AC Specifications for PB2 and Late Write SRAMs
L3CHDV
L3DVEH
Parity Inputs
and t
and t
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
L3CLDV
L3DVEL
as drawn here are negative numbers, that is, input setup time is
as drawn here will be negative numbers, that is, output valid time will be
VM
t
L3CHOV
Figure 12
VM = Midpoint Voltage (GV
t
L3CHDV
t
L3CHDX
VM
and the loading of
t
t
L3DVEH
L3DXEH
VM
t
L3CHOX
VM
t
L3CHOZ
t
L3DVEL
DD
/2)
Figure
VM
VM
t
L3CLDV
8.
Electrical and Thermal Characteristics
t
L3CLDX
t
VM
L3CLDZ
VM
t
L3DXEL
VM
VM
Figure
11,
29