KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 54

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

System Design Information
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
9.4
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV
to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
MPC7457. If the L3 interface is not used, GV
L3VSEL should be connected to BVSEL; the remainder of the L3 interface may be left unterminated.
9.5
The MPC7457 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature.
To measure Z
each resistor is varied until the pad voltage is OV
The output impedance is the average of two components, the resistances of the pull-up and pull-down
devices. When data is held low, SW2 is closed (SW1 is open), and R
pad equals OV
SW1 is closed (SW2 is open), and R
becomes the resistance of the pull-up devices. R
Then, Z
Table 21
and is relatively unaffected by bus voltage.
54
0
summarizes the signal impedance results. The impedance increases with junction temperature
= (R
Connection Recommendations
Output Buffer DC Impedance
0
P
, an external resistor is connected from the chip pad to OV
DD
+ R
/2. R
N
)/2.
N
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
then becomes the resistance of the pull-down devices. When data is held high,
Figure 25. Driver Impedance Measurement
Data
P
is trimmed until the voltage at the pad equals OV
DD
P
should be connected to the OV
DD
and R
/2 (see
DD
. Unused active high inputs should be connected
N
are designed to be close to each other in value.
Pad
Figure
R
R
OGND
OV
N
P
DD
DD
, OV
25).
SW2
SW1
N
DD
is trimmed until the voltage at the
, GV
DD
or GND. Then, the value of
DD
DD
, and GND pins in the
power plane, and
Freescale Semiconductor
DD
/2. R
P
then