KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 26

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KMC7457VG1267LC

Manufacturer Part Number
KMC7457VG1267LC
Description
IC MPU RISC 32BIT 1267MHZ 483BGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of KMC7457VG1267LC

Processor Type
MPC74xx PowerPC 32-Bit
Speed
1.267GHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
483-FCCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KMC7457VG1267LC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical and Thermal Characteristics
window at the internal receiving latches. This delayed clock is used to capture the data into these latches
which comprise the receive FIFO. This clock is asynchronous to all other processor clocks. This latched
data is subsequently read out of the FIFO synchronously to the processor clock. The time between writing
and reading the data is set by the using the sample point settings defined in the L3CR register.
Table 13
Figure
26
At recommended operating conditions. See
L3_CLK rise and fall time
Setup times: Data and parity
Input hold times: Data and parity
Valid times: Data and parity
Valid times: All other outputs
Output hold times: Data and parity
Output hold times: All other outputs
L3_CLK to high impedance: Data
and parity
9, assuming the timing relationships shown in
provides the L3 bus interface AC timing specifications for the configuration as shown in
Parameter
Table 13. L3 Bus Interface AC Timing Specifications for MSUG2
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
t
L3CR
Table
t
t
Symbol
t
t
t
t
t
t
t
t
t
L3CHDX
L3DVEH
L3DXEH
L3CHDV
L3CHOV
L3CLDX,
L3CHOX
L3DVEL
L3DXEL
L3CLDV
L3CLDZ
, t
4.
L3CF
,
,
,
,
(– t
Rev 1.2 (1.5-V I/O Mode)
Rev 1.1. (All I/O Modes)
(t
(t
(t
L3CLK
L3CLK
L3CLK
+ 0.90
+ 0.85
– 0.60
– 0.50
L3CLK
Min
/4)
/4)
/4)
/4)
Device Revision (L3 I/O Voltage)
Figure 10
(– t
(– t
(t
L3CLK
+ 0.60
+ 0.65
+ 0.60
L3CLK
L3CLK
Max
0.75
/4)
/4)
/4)
and the loading shown in
(– t
(t
(t
(t
(1.8-, 2.5-V I/O Modes)
L3CLK
L3CLK
L3CLK
+ 0.70
+ 0.70
– 0.50
– 0.50
L3CLK
Min
/4)
/4)
/4)
/4)
Rev 1.2
(– t
(– t
9
(t
L3CLK
+ 0.50
+ 0.65
+ 0.60
L3CLK
L3CLK
Max
0.75
Freescale Semiconductor
/4)
/4)
/4)
Figure
Unit
ns
ns
ns
ns
ns
ns
ns
ns
8.
Notes
2, 3, 4
5, 7, 8
5, 7, 8
5, 6,
5, 6,
2, 4
7, 8
7, 8
1

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