KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 27

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
At recommended operating conditions. See
L3_CLK to high impedance: All
other outputs
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in
4. t
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in
7. t
8. Assumes default value of L3OHCR. See
9. L3 I/O voltage mode must be configured by L3VSEL as described in
or falling edge of the input L3_ECHO_CLKn (see
input setup time specifications, this will be treated as negative input setup time.
valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising) edges
of L3_ECHO_CLKn at any frequency.
L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a
purely resistive 50-Ω load (see
valid time specifications, this will be treated as negative output valid time.
by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid and output hold
times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock
before the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
information.
selected as specified in
L3_CLK
L3_CLK
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the MPC7457 can latch an input signal that is
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
Parameter
Table 13. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)
Table
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
4. See
Figure
Table
Symbol
t
L3CHOZ
Table 23
8).
Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC
4.
for revision level information and part marking.
Rev 1.2 (1.5-V I/O Mode)
Rev 1.1. (All I/O Modes)
Figure
Min
—
10). Input timings are measured at the pins.
Device Revision (L3 I/O Voltage)
(t
L3CLK
+ 0.65
Table
Max
/4)
3, and voltage supplied at GV
Figure
(1.8-, 2.5-V I/O Modes)
DD
Min
—
.
10. For consistency with other output
Figure
Electrical and Thermal Characteristics
Rev 1.2
10. For consistency with other
9
(t
L3CLK
+ 0.65
Max
Specifications,” for more
/4)
DD
must match mode
Unit
ns
Notes
27