KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 19

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 4
Freescale Semiconductor
At recommended operating conditions. See
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
2. The symbology used for timing specifications herein follows the pattern of t
3. t
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high
5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Timing
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters
sysclk
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50-Ω load (see
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
t
relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t
SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that
the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state
for inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
before returning to high impedance as shown in
than the minimum t
the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for
precharge.The high-impedance behavior is guaranteed by design.
AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it
low in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second
cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 t
impedance as shown in
hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle
(crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is 1.0
t
represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These
inputs must remain stable after the second sample. See
(reference)(state)(signal)(state)
SYSCLK
is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
provides the AC test load for the MPC7457.
. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).
SYSCLK
Table 9. Processor Bus AC Timing Specifications
Parameter
Output
Figure 6
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
for outputs. For example, t
period, to ensure that another master asserting TS on the following clock will not contend with
before the first opportunity for another master to assert ARTRY. Output valid and output
Table
4.
Z
0
Figure 4. AC Test Load
= 50 Ω
Figure
IVKH
6. The nominal precharge width for TS is 0.5 × t
Figure 5
symbolizes the time input signals (I) reach the valid state (V)
Symbol
t
KHARPZ
for sample timing.
Figure
2
R
(signal)(state)(reference)(state)
L
= 50 Ω
4). Input and output timings are measured at
All Revisions and
Min
Speed Grades
—
1
SYSCLK
(continued)
Electrical and Thermal Characteristics
OV
KHOV
; that is, it should be high
DD
Max
/2
2
symbolizes the time from
for inputs and
SYSCLK
t
SYSCLK
Unit
, that is, less
Notes
3, 5,
6, 7
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