KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 22

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Electrical and Thermal Characteristics
The L3_CLK timing diagram is shown in
22
At recommended operating conditions. See
L3 clock jitter
Notes:
1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals which
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data, and
6. L3 I/O voltage mode must be configured by L3VSEL as described in
AC
minimum L3 clock frequency and period are f
are common to both SRAM chips in the L3.
Late Write SRAM. This parameter is critical to the read data signals because the processor uses the feedback loop to latch
data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.
control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the
L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage
noise or thermal effects. This is also comprehended in the AC timing specifications and need not be considered in the L3
timing analysis.
mode selected as specified in
Specifications,” for an explanation that this maximum frequency is not functionally tested at speed by Freescale. The
For PB2 or Late Write:
L3_ECHO_CLK1
L3_ECHO_CLK3
Parameter
L3_CLK0
L3_CLK1
Table 10. L3_CLK Output AC Timing Specifications (continued)
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Table
Figure 7. L3_CLK_OUT Output Timing Diagram
Table
4. See
VM
VM
VM
VM
Symbol
t
CHCL
4.
Table 23
t
SYSCLK
L3_CLK
Figure
VM
VM
VM
VM
Rev 1.2 (1.5-V I/O Mode)
Rev 1.1. (All I/O Modes)
for revision level information and part marking.
and t
Min
—
7.
SYSCLK
Device Revision (L3 I/O Voltage)
Typ
—
VM
VM
VM
VM
, respectively.
Table
Max
± 75
3, and voltage supplied at GV
(1.8-, 2.5-V I/O Modes)
t
Min
L3CR
—
Rev 1.2
Typ
—
VM
VM
VM
t
t
t
L3CSKW2
L3CSKW2
L3CSKW1
6
Section 5.2.3, “L3 Clock
Freescale Semiconductor
Max
± 75
DD
Unit
t
must match
L3CF
ps
Notes
5