KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 23

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.2.4
The MPC7457 L3 interface supports three different types of SRAM: source-synchronous, double data rate
(DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each requires a different
protocol on the L3 interface and a different routing of the L3 clock signals. The type of SRAM is
programmed in L3CR[22:23] and the MPC7457 then follows the appropriate protocol for that type. The
designer must connect and route the L3 signals appropriately for each type of SRAM. Following are some
observations about the L3 interface.
In general, if routing is short, delay-matched, and designed for incident wave reception and minimal
reflection, there is a high probability that the AC timing of the MPC7457 L3 interface will meet the
maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic,
guard-banded AC specifications (see
testers described in
which inevitably make worst-case critical path timing analysis pessimistic.
More specifically, certain signals within groups should be delay-matched with others in the same group
while intergroup routing is less critical. Only the address and control signals are common to both SRAMs
and additional timing margin is available for these signals. The double-clocked data signals are grouped
with individual clocks as shown in
for the MSUG2 DDR SRAM (see
coupled group of outputs from the MPC7457; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0]
form a closely coupled group of inputs.
The MPC7450 RISC Microprocessor Family User’s Manual refers to logical settings called ‘sample
points’ used in the synchronization of reads from the receive FIFO. The computation of the correct value
for this setting is system-dependent and is described in the MPC7450 RISC Microprocessor Family User’s
Manual. Three specifications are used in this calculation and are given in
three specifications are included in the calculations to determine the sample points, as incorrect settings
can result in errors and unpredictable behavior. For more information, see the MPC7450 RISC
Microprocessor Family User’s Manual.
Freescale Semiconductor
•
•
•
•
•
•
The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and
L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched.
For 1-Mbyte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)
For 2-Mbyte of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)
For 4-Mbyte of SRAM, use L3_ADDR[18:0] (L3_ADDR[0] is LSB)
No pull-up resistors are required for the L3 interface
For high-speed operations, L3 interface address and control signals should be a ‘T’ with minimal
stubs to the two loads; data and clock signals should be point-to-point to their single load.
shows the AC test load for the L3 interface.
L3 Bus AC Specifications
Section 5.2.3, “L3 Clock AC
Output
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Figure 8. AC Test Load for the L3 Interface
Figure
Figure 9
Table
Z
0
9); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely
= 50 Ω
12,
or
Figure
Table
Specifications,” and the uncertainty of clocks and signals
13, and
11, depending on the type of SRAM. For example,
Table
R
L
= 50 Ω
14), the limitations of functional
Table
Electrical and Thermal Characteristics
GV
DD
11. It is essential that all
/2
Figure 8
23