KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 25

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.2.4.2
When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in
Outputs from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to
SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock
output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid
times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period
before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control,
data, and L3_CLKn signals have propagated across the printed-wiring board.
Inputs to the MPC7457 are source-synchronous with the CQ clock generated by the DDR MSUG2
SRAMs. These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7457. An internal
circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data
Freescale Semiconductor
At recommended operating conditions. See
Notes:
1. See the MPC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.
2. See
3. Approximate delay verified by simulation; not tested or characterized.
4. Default value.
5. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times of
all signals latched relative to that clock signal by the SRAM; see
Field Name
L3CLKn_OH
L3DOHn
Table 13
L3 Bus AC Specifications for DDR MSUG2 SRAMs
1
and
Table 14
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing (continued)
All signals latched by
SRAM connected to
Affected Signals
L3_DATA[n:n+7],
L3_DP[n/8]
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
L3_CLKn
for more information.
Table
4.
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
0b000
0b001
0b010
0b011
0b100
0b101
0b111
0b111
Value
Parameter
Symbol
t
t
t
t
t
L3CHOV
L3CHDV
L3CHDV
Output Valid Time
L3CLDV
L3CLDV
,
,
,
2
Figure 9
Change
– 100
– 150
– 200
– 250
– 300
– 350
+ 100
+ 150
+ 200
+ 250
+ 300
+ 350
– 50
+ 50
0
0
and
3
Figure
Parameter
Symbol
t
t
t
t
t
L3CHOX
L3CHDX
L3CHDX
Output Hold Time
L3CLDX
L3CLDX
11.
Electrical and Thermal Characteristics
,
,
,
2
Change
– 100
– 150
– 200
– 250
– 300
– 350
+ 100
+ 150
+ 200
+ 250
+ 300
+ 350
– 50
+ 50
0
0
3
Unit
ps
ps
Figure
Notes
4
5
5
5
5
5
5
5
4
9.
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