KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 24

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Electrical and Thermal Characteristics
5.2.4.1
The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register (L3OCHR).
Each field controls the timing for a group of signals. The AC timing specifications presented herein
represent the AC timing when the register contains the default value of 0x0000_0000. Incrementing a field
delays the associated signals, increasing the output valid time and hold time of the affected signals. In the
special case of delaying an L3_CLK signal, the net effect is to decrease the output valid and output hold
times of all signals being latched relative to that clock signal. The amount of delay added is summarized
in
parameters of the L3 bus in any way.
24
At recommended operating conditions. See
Delay from processor clock to internal_L3_CLK
Delay from internal_L3_CLK to L3_CLK[n] output pins
Delay from L3_ECHO_CLK[n] to receive latch
Notes:
1. This specification describes a logical offset between the internal clock edge used to launch the L3 address and control signals
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising or falling
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid and ready to be sampled from
Table
(this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used to launch the L3_CLK[n]
signals. With proper board routing, this offset ensures that the L3_CLK[n] edge will arrive at the SRAM within a valid address
window and provide adequate setup and hold time. This offset is reflected in the L3 bus interface AC timing specifications,
but must also be separately accounted for in the calculation of sample points and, thus, is specified here.
edge at the L3CLK[n] pins.
the FIFO.
Field Name
L3AOH
12. Note that these settings affect output timing parameters only and do not impact input timing
Effects of L3OHCR Settings on L3 Bus AC Specifications
1
Affected Signals
L3_ADDR[18:0],
L3_CNTL[0:1]
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Table 11. Sample Points Calculation Parameters
Parameter
Table
4.
Value
0b00
0b01
0b10
0b11
Parameter
Symbol
t
Output Valid Time
L3CHOV
2
Change
+100
+150
+50
0
3
Parameter
Symbol
Symbol
t
L3CHOX
Output Hold Time
t
t
t
ECI
CO
AC
2
Change
+100
+150
Max
+50
3/4
Freescale Semiconductor
3
3
0
3
t
L3_CLK
Unit
Unit
ns
ns
ps
Notes
Notes
1
2
3
4