KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 4

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Features
4
•
— Four integer units (IUs) that share 32 GPRs for integer operands
— Five-stage FPU and a 32-entry FPR file
— Four vector units and 32-entry vector register file (VRs)
— Three-stage load/store unit (LSU)
Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
— Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2
— A maximum of three instructions can be dispatched to the issue queues per clock cycle
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
– IU2 executes miscellaneous instructions including the CR logical operations, integer
– Fully IEEE 754-1985 compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
– Vector floating-point unit (VFPU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
– Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle
– Four-cycle FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated adder calculates effective addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
multiply, divide, and move to/from special-purpose register instructions
multiplication and division instructions, and move to/from special-purpose register
instructions
vector add instructions (for example, vaddsbs, vaddshs, and vaddsws)
vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and
vmladduhm)
operations
throughput
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Freescale Semiconductor