KMC7457VG1267LC Freescale Semiconductor, KMC7457VG1267LC Datasheet - Page 7

• Manufacturer Part Number: KMC7457VG1267LC
• Description: IC MPU RISC 32BIT 1267MHZ 483BGA
• Manufacturer: Freescale Semiconductor

Specifications of KMC7457VG1267LC

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.267GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 483-FCCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
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— Store merging for multiple store misses to the same line. Only coherency action taken
— Three-entry finished store queue and five-entry completed store queue between the LSU and
— Separate additional queues for efficient buffering of outbound data (such as castouts and
Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
Power and thermal management
— 1.3-V processor core
— The following three power-saving modes are available to the system:
— Thermal management facility provides software-controllable thermal management. Thermal
— Instruction cache throttling provides control of instruction fetching to limit power consumption
Performance monitor can be used to help debug system designs and improve software efficiency
In-system testability and debugging features through JTAG boundary-scan capability
Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only
Reliability and serviceability
— Parity checking on system bus and L3 cache bus
— Parity checking on the L2 and L3 cache tag arrays
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).
the L1 data cache
write-through stores) from the L1 data cache and L2 cache
other multiprocessor operations
– Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the
– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system
management is performed through the use of three supervisor-level registers and an
MPC7457-specific thermal management exception.
JTAG logic remain running. The part goes into the doze state to snoop memory operations
on the bus and back to nap using a QREQ/QACK processor-system handshake protocol.
PLL in a locked and running state. All internal functional units are disabled.
can then disable the SYSCLK source for greater system power savings. Power-on reset
procedures for restarting and relocking the PLL must be followed on exiting the deep sleep
state.
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 7
Features
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