MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 112

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Bus Operation
so the CPU32+ performs a CPU space type 3 write with the interrupt mask level (I2–I0)
encoded on bits 2–0 of the data bus, as shown in the following figure. The CPU space type
3 cycle waits for the bus to be available, and is shown externally to indicate to external
devices that the QUICC is going into LPSTOP mode. If an external device requires addi-
tional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT.
The SIM60 provides internal DSACKx response to this cycle. For more information on how
the SIM60 responds to LPSTOP mode, see Section 6 System Integration Module (SIM60)
for details.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
I2
I1
I0
4.4.3 Module Base Address Register (MBAR) Access
All internal module registers, including the SIM60, occupy a single 8-kbyte block that is locat-
able along 8-kbyte boundaries. The location is fixed by writing the desired base address of
the SIM60 block to the MBAR using the MOVES instruction. The MBAR is only accessible
in CPU space at address $0003FF00. The SFC or DFC register must indicate CPU space
(FC2–FC0 = $7), using the MOVEC instruction, before accessing MBAR. Refer to Section
6 System Integration Module (SIM60) for additional information on the MBAR.
4.4.4 Interrupt Acknowledge Bus Cycles
The CPU32+ makes an interrupt pending in three cases. The first case occurs when a
peripheral device signals the CPU32+ (with the IRQ7–IRQ1 signals) that the device requires
service and the internally synchronized value on these signals indicates a higher priority
than the interrupt mask in the status register. The second case occurs when a transition has
occurred in the case of a level 7 interrupt. A recognized level 7 interrupt must be removed
for one clock cycle before a second level 7 can be recognized. The third case occurs if, upon
returning from servicing a level 7 interrupt, the request level stays at 7 and the processor
mask level changes from 7 to a lower level, a second level 7 is recognized. The CPU32+
takes an interrupt exception for a pending interrupt within one instruction boundary (after
processing any other pending exception with a higher priority). The following paragraphs
describe the various kinds of interrupt acknowledge bus cycles that can be executed as part
of interrupt exception processing.
4.4.4.1 INTERRUPT ACKNOWLEDGE CYCLE—TERMINATED NORMALLY. When the
CPU32+ processes an interrupt exception, it performs an interrupt acknowledge cycle to
obtain the number of the vector that contains the starting location of the interrupt service rou-
tine. Some interrupting devices have programmable vector registers that contain the inter-
rupt vectors for the routines they use. The following paragraphs describe the interrupt
acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply
a vector number and use the autovector cycle described in 4.4.4.2 Autovector Interrupt
Acknowledge Cycle.
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