MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 275

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

ASTM—Arbitration Synchronous Timing Mode
FRZ1—Freeze SWT and PIT Enable
FRZ0—Freeze Bus Monitor Enable
BCLROID2–BCLROID0—Bus Clear Out Arbitration ID
SHEN1–SHEN0—Show Cycle Enable
MOTOROLA
This bit determines whether the EBI will synchronize the arbitration signals: BR, BG, and
BGACK. The synchronization will add a one-clock delay to the external bus arbitration.
These bits contain the arbitration priority level for the assertion of the BCLRO signal.
When internal masters (IDMA, SDMA, or DRAM refresh cycle) request the bus and the
arbitration level on the IMB is greater than the bus clear out arbitration ID, the BCLRO sig-
nal will be asserted until the arbitration level is less than or equal to the bus clear out ar-
bitration ID. BCLRO can be used to clear an external master from the external bus when
a refresh cycle is pending. It may also be used to clear an external master from the bus
when an SDMA or IDMA channel requests the external bus.
These two control bits determine what the EBI does with the external bus during internal
transfer operations (see Table 6-3). A show cycle allows internal transfers to be externally
monitored. The address, data, and control signals (except for AS) are driven externally.
DS is used to signal address strobe timing for show cycles. Data is valid on the next falling
clock edge after DS is negated. However, data is not driven externally and AS and DS are
not asserted externally for internal accesses unless show cycles are enabled.
If external bus arbitration is disabled, the EBI will not recognize an external bus request
until arbitration is enabled again. When SHEN1 is set, an external bus request causes an
internal master to stop its current cycle and relinquish the internal bus. The internal master
resumes running cycles on the bus after BR and BGACK are negated. To prevent bus
0 = Asynchronous timing on the arbitration signals may be used. The arbitration sig-
1 = Synchronous timing on the arbitration signals must be used. The arbitration control
0 = When FREEZE is asserted, the SWT and the PIT counters continue to run. See
1 = When FREEZE is asserted, the SWT and the PIT counters are disabled, prevent-
0 = When FREEZE is asserted, the bus monitor continues to operate as programmed.
1 = When FREEZE is asserted, both the internal and external bus monitors are dis-
nals will be synchronized internally by the QUICC and do not have to meet any tim-
ings relative to the system clock.
signals will not be synchronized internally and therefore must meet the system
clock setup and hold timings.
6.3.3 Freeze Support for more information.
ing interrupts from occurring during software debugging.
abled.
Program this value to 3 in a normal system to allow the SDMA
and DRAM refresh controller to clear other bus masters off the
external bus.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
System Integration Module (SIM60)
6-31