MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 185

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
CPU32+
The vector number for the TRAP instruction is internally generated—part of the number
comes from the instruction itself. The trap vector number, PC value, and a copy of the SR
are saved on the supervisor stack. The saved PC value is the address of the instruction that
follows the instruction that generated the trap. For all instruction traps other than TRAP, a
pointer to the instruction causing the trap is also saved in the fifth and sixth words of the
exception stack frame.
5.5.2.5 SOFTWARE BREAKPOINTS. To support hardware emulation, the CPU32+ must
provide a means of inserting breakpoints into target code and of announcing when a break-
point is reached.
The MC68000 and MC68008 can detect an illegal instruction inserted at a breakpoint when
the processor fetches from the illegal instruction exception vector location. Since the VBR
on the CPU32+ allows relocation of exception vectors, the exception vector address is not
a reliable indication of a breakpoint. CPU32+ breakpoint support is provided by extending
the function of a set of illegal instructions ($4848–$484F).
When a breakpoint instruction is executed, the CPU32+ performs a read from CPU space
$0, at a location corresponding to the breakpoint number. If this bus cycle is terminated by
BERR, the processor performs illegal instruction exception processing. If the bus cycle is
terminated by DSACKx, the processor uses the data returned to replace the breakpoint in
the instruction pipeline and begins execution of that instruction. See Section 4 Bus Opera-
tion for a description of CPU space operations.
5.5.2.6 HARDWARE BREAKPOINTS. The CPU32+ recognizes hardware breakpoint
requests. Hardware breakpoint requests do not force immediate exception processing, but
are left pending. An instruction breakpoint is not made pending until the instruction corre-
sponding to the request is executed.
A pending breakpoint can be acknowledged between instructions or at the end of exception
processing. To acknowledge a breakpoint, the CPU performs a read from CPU space $0 at
location $1E (see Section 4 Bus Operation).
If the bus cycle terminates normally, instruction execution continues with the next instruction
as if no breakpoint request occurred. If the bus cycle is terminated by BERR, the CPU
begins exception processing. Data returned during this bus cycle is ignored.
Exception processing follows the regular sequence. Vector number 12 (offset $30) is inter-
nally generated. The PC of the executing instruction, the PC of the next instruction to be exe-
cuted, and a copy of the SR are saved on the supervisor stack.
5.5.2.7 FORMAT ERROR. The processor checks certain data values for control operations.
The validity of the stack format code and, in the case of a bus cycle fault format, the version
number of the processor that generated the frame are checked during execution of the RTE
instruction. This check ensures that the program does not make erroneous assumptions
about information in the stack frame.
If the format of the control data is improper, the processor generates a format error excep-
tion. This exception saves a four-word format exception frame and then vectors through vec-
MOTOROLA
MC68360 USER’S MANUAL
5-43
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