MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 488

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
A—Address
CM—Continuous Mode
P—Preamble
NS—No Stop Bit Transmitted
CT—CTS Lost
Data Length
Tx Data Buffer Pointer
7.10.16.18 UART EVENT REGISTER (SCCE). The SCCE is called the UART event regis-
ter when the SCC is operating as a UART. It is a 16-bit register used to report events rec-
ognized by the UART channel and to generate interrupts. On recognition of an event, the
UART controller will set the corresponding bit in the UART event register. Interrupts gener-
ated by this register may be masked in the UART mask register. An example of interrupts
that may be generated by the UART is shown in Figure 7-49.
7-164
This bit is valid only in multidrop mode (either automatic or non-automatic).
The data length is the number of octets that the CP should transmit from this BD’s data
buffer. It is never modified by the CP. Normally, this value should be greater than zero.
The data length may be equal to zero with the P-bit set, and only a preamble will be sent.
The transmit buffer pointer, which always points to the first location of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory.
0 = This buffer contains data only.
1 = Set by the CPU32+ core, this bit indicates that this buffer contains address char-
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
0 = No preamble sequence is sent.
1 = The UART sends one character of all ones before sending the data so that the oth-
0 = Normal operation. Stop bits are sent with all characters in this buffer.
1 = The data in this buffer will be sent without stop bits if the SYNC mode is selected
The following bit is written by the CP after it has finished transmitting the associated
0 = The CTS signal remained asserted during transmission.
1 = The CTS signal was negated during transmission.
acter(s). All the buffer’s data will be transmitted as address characters.
data buffer to be retransmitted automatically when the CP next accesses this BD.
However, the R-bit will be cleared if an error occurs during transmission, regard-
less of the CM bit.
er end will detect an idle line before the data. If this bit is set and the data length of
this BD is zero, only a preamble will be sent.
by setting the SYN bit in the PSMR. If ASYNC is selected the stop bit is SHAVED
according to the value of the DSR register.
data buffer.
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