MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 428
MC68MH360ZP33L
Manufacturer Part Number
MC68MH360ZP33L
Description
IC MPU 32BIT QUICC 357-PBGA
Manufacturer
Freescale Semiconductor
Specifications of MC68MH360ZP33L
Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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Baud Rate Generators (BRGs)
Refer to Figure 7-36 for the BRG block diagram.
The clock input to the prescaler may be selected by the EXTC bits to come from one of three
sources: BRGCLK, CLK2, or CLK6. Each source is discussed in the following paragraphs.
The BRGCLK is generated in the QUICC clock synthesizer specifically for the four BRGs
(as well as a fifth BRG that is part of the SPI) and defaults to the system frequency (e.g., 25
MHz). However, the clock synthesizer in the SIM60 has an option to divide the BRGCLK by
1, 4, 16, or 64 before it leaves the clock synthesizer. Whatever the resulting frequency of
BRGCLK, the user may use that frequency as the input to the QUICC BRGs.
The ability to reduce the frequency of BRGCLK before it leaves the clock synthesizer is use-
ful in low-power applications. In a low-power mode, the BRG clocking could be a significant
factor in overall QUICC power consumption. Thus, if the BRGs do not need to generate high
frequencies or do not require a high resolution in the user application, a lower frequency
BRGCLK may be input to the BRGs. The user may wish to dynamically change the general
system clock frequency in the clock synthesizer (slow go mode) while still having the BRG
run at the original frequency. The BRGCLK allows this option also.
Alternatively, the user may choose the CLK2 or CLK6 pins to be the clock source. An exter-
nal pin allows flexible baud rate frequency generation, regardless of the system frequency.
Additionally, the CLK2 or CLK6 pins allow a single external frequency to become the input
7-104
• Each BRG Output May Be Routed to a Pin (e.g., BRGO1)
BRGCLK
RXD1
CLK6
CLK2
The BRG configuration register may be written at any time, re-
gardless of the BRGCLK input frequency.
Figure 7-36. Baud Rate Generator Block Diagram
EXTC
MUX
Freescale Semiconductor, Inc.
AUTOBAUD
CONTROL
For More Information On This Product,
ATB
MC68360 USER’S MANUAL
Go to: www.freescale.com
PRESCALER
DIVIDE BY
1 OR 16
DIV16
NOTE
COUNTER
CD11–CD0
1–4096
12-BIT
BRGO1
CLOCK
TO PIN
AND/OR
BANK
OF CLOCKS
MOTOROLA
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