MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 679

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

W—Wrap (Final BD in Table)
I—Interrupt
C—Control Character
CM—Continuous Mode
SL—Silence
7.13.8.23 CENTRONICS RECEIVER EVENT REGISTER (PIPE). When the Centronics
Receiver protocol is selected, the SMC2 event register is called the Centronics Receiver
event register. It is an 8-bit register which is used to report events recognized by the Cen-
tronics channel and generate interrupts. On recognition of an event, the Centronics control-
ler will set its corresponding bit in the Centronics event register.
The Centronics event register is a memory-mapped register that may be read at any time.
A bit is cleared by writing a one (writing a zero does not affect a bit’s value). More than one
bit may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request. This register is cleared at reset.
CCR—Control Character Received
BSY—Busy Condition
MOTOROLA
The buffer was closed due to the expiration of the programmable silence period timer (de-
fined in MAX_SL).
A control character was received (with reject (R) character = 1) and stored in the Receive
Control Character Register (RCCR).
A character was received and discarded due to lack of buffers. Reception continues as
soon as an empty buffer is provided.
0 = This is not the last buffer descriptor in the Rx BD Table.
1 = This is the last buffer descriptor in the Rx BD Table. After this buffer has been used,
0 = No interrupt is generated after this buffer has been filled.
1 = The RX bit in the Centronics event register will be set when this buffer has been
0 = This buffer does not contain a control character.
1 = This buffer contains a control character. The last byte in the buffer is one of the user
0 = Normal Operation.
1 = The E-bit is not cleared by the CP after this buffer is closed, allowing the associated
the CP will receive incoming data into the first BD in the table (the BD pointed to
by RBASE). The number of Rx BDs in this table is programmable, and is deter-
mined only by the wrap bit and the overall space constraints of the dual-port RAM.
completely filled by the CP, indicating the need for the CPU32+ core to process the
buffer. The RX bit can cause an interrupt if it is enabled.
defined control characters.
data buffer to be overwritten automatically when the CP next accesses this BD.
Freescale Semiconductor, Inc.
7
–
For More Information On This Product,
6
–
MC68360 USER’S MANUAL
Go to: www.freescale.com
5
–
4
–
CCR
3
BSY
2
CHR
1
RX
0
Parallel Interface Port (PIP)
7-355