MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 558

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
7-234
5. Connect the CLK7 pin to SCC4 using the SI. Write the R4CS bits in SICR to 110.
6. Connect the SCC4 to the NMSI (i.e., its own set of pins). Clear the SC4 bit
7. Write $0740 to the SDCR to initialize the SDMA Configuration Register.
8. Write RBASE and TBASE in the SCC parameter RAM to point to the Rx BD and Tx
9. Program the CR to execute the INIT RX & TX PARAMS command for this channel.
10. Write RFCR with $18 and TFCR with $18 for normal operation.
11. Write MRBLR with the maximum number of bytes per receive buffer. For this case,
12. Write CRC_P with $0000FFFF to comply with the 16-bit CRC-CCITT.
13. Write CRC_C with $0000F0B8 to comply with the 16-bit CRC-CCITT.
14. Initialize the Rx BD. Assume the Rx data buffer is at $00001000 in main memory.
15. Initialize the Tx BD. Assume the Tx data buffer is at $00002000 in main memory
16. Write $FFFF to the SCCE to clear any previous events.
17. Write $0013 to the SCCM to enable the TXE, TX, and RX interrupts.
18. Write $08000000 to the CIMR to allow SCC4 to generate a system interrupt. (The
19. Write $00001980 to GSMR_H4 to configure the transparent channel.
20. Write $00000000 to GSMR_L4 to configure the CTS and CD pins to automatically
21. Write $00000030 to GSMR_L4 to enable the SCC4 transmitter and receiver. This
PADIR bit 14 with a zero.
Write the T4CS bits in SICR to 110.
in the SICR.
BD in the dual-port RAM. Assuming one Rx BD at the beginning of dual-port RAM,
and one Tx BD following that Rx BD, write RBASE with $0000 and TBASE with
$0008.
For instance, to execute this command for SCC1, write $0001 to the CR. This com-
mand causes the RBPTR and TBPTR parameters of the serial channel to be updated
with the new values just programmed into RBASE and TBASE.
assume 16 bytes, so MRBLR = $0010.
Write $B000 to Rx_BD_Status. Write $0000 to Rx_BD_Length (not required—done
for instructional purposes only). Write $00001000 to Rx_BD_Pointer.
and contains five 8-bit characters. Write $BC00 to Tx_BD_Status. Write $0005 to
Tx_BD_Length. Write $00002000 to Tx_BD_Pointer.
CICR should also be initialized.)
control transmission and reception (DIAG bits). Normal operation of the transmit
clock is used (TCI is cleared). Notice that the transmitter (ENT) and receiver (ENR)
have not been enabled yet.
additional write ensures that the ENT and ENR bits will be enabled last.
After 5 bytes have been transmitted, the Tx BD is closed. Addi-
tionally, the receive buffer is closed after 16 bytes have been re-
ceived. Any additional receive data beyond 16 bytes will cause
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NOTE
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