MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 391

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Serial Interface with Time Slot Assigner
gram the transmit routing, and the other SI RAM is always used to program the receive rout-
ing. With the SI RAMs, the user can define the number of bits/bytes that are to be routed to
which SCC or SMC and the times the external strobes are to be asserted and negated. The
size of the SI RAM that is available for time-slot programming depends on the configuration.
If two TDM channels are selected, the SI RAM entries available per channel are reduced by
one-half. If on-the-fly changes are also allowed, the SI RAM entries are further reduced by
one-half. Even in a configuration with two TDM channels and on-the-fly changes allowed,
the SI RAM size is still sufficient to allow extensive time-slot programming flexibility. The
maximum frame length that can be supported in any configuration is 8192 bits.
The SI supports two testing modes: echo and loopback. Echo mode provides a return signal
from the physical interface by retransmitting the signal it has received. The physical interface
echo mode differs from the individual SCC echo mode in that it can operate on the entire
TDM signal rather than just on a particular SCC channel. Loopback mode causes the phys-
ical interface to receive the same signal it is transmitting. The SI loopback mode checks
more than the individual SCC loopback; it checks the SI and the internal channel routes.
The maximum clock that can be input to the TSA depends on the internal SyncCLK rate.
SyncCLK, which is generated in the QUICC clock synthesizer specifically for the SCCs,
SMCs, and TSA, defaults to the system frequency (for instance, 25 MHz). However, the
clock synthesizer in the SIM60 has an option to divide SyncCLK by 1, 4, 16, or 64 before it
leaves the clock synthesizer. Whatever the resulting frequency of SyncCLK, the maximum
external serial clock that may be an input to the TSA is SyncCLK/2.5.
The ability to reduce the frequency of SyncCLK before it ever leaves the clock synthesizer
is useful for two reasons. First, in a low-power mode, the TSA clocking could potentially be
a significant factor in overall QUICC power consumption. Thus, if the TSA does not need to
operate at high frequencies, the user may choose a lower frequency SyncCLK as the input
to the TSA. (In making this decision, the user must also consider the needs of the other
SCCs and SMCs not connected to the TSA and select a sufficiently high SyncCLK value for
their use.) Second, the user may wish to dynamically change the general system clock fre-
quency in the clock synthesizer (slow-go mode) while still having the TSA run at the original
frequency. The SyncCLK also allows this configuration.
If an SCC or SMC is operating with the NMSI, then the serial clock rate may be slightly
faster, at a value not to exceed SyncCLK/2.
7.8.3 Enabling Connections to the TSA
Each SCC and SMC may be independently enabled to be connected to the TSA (see Figure
7-22). Note that separate bits enable whether each SCC or SMC is connected to the TSA
or to its own set of external pins. Additionally, the two TDM interfaces must be enabled to
be connected to the TSA.
MOTOROLA
MC68360 USER’S MANUAL
7-67
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