IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 10

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Figure 49. Transmit Bit Offset in E1 Mode - 2 ............................................................................................................................................................. 66
Figure 50. Transmit Bit Offset in E1 Mode - 3 ............................................................................................................................................................. 67
Figure 51. Transmit Bit Offset in E1 Mode - 4 ............................................................................................................................................................. 67
Figure 52. Transmit Bit Offset in E1 Mode - 5 ............................................................................................................................................................. 68
Figure 53. E1 To T1/J1 Format Conversion ................................................................................................................................................................ 70
Figure 54. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 1 ...................................................................................... 71
Figure 55. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 2 ...................................................................................... 71
Figure 56. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 3 ...................................................................................... 72
Figure 57. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 1 .............................................................................. 72
Figure 58. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 2 .............................................................................. 73
Figure 59. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 3 .............................................................................. 73
Figure 60. T1/J1 Transmit Clock Master Mode - Functional Timing Example ............................................................................................................. 74
Figure 61. T1/J1 Transmit Multiplexed Mode - Functional Timing Example 1 ............................................................................................................. 75
Figure 62. T1/J1 Transmit Multiplexed Mode - Functional Timing Example 2 ............................................................................................................. 76
Figure 63. Transmit Bit Offset in T1/J1 Mode - 1 ......................................................................................................................................................... 77
Figure 64. Transmit Bit Offset in T1/J1 Mode - 2 ......................................................................................................................................................... 77
Figure 65. E1 Mode Jitter Tolerance (N1 = N2 = 2fH) ................................................................................................................................................. 85
Figure 66. E1 Mode Jitter Transfer (N1 = N2 = 2fH) .................................................................................................................................................... 85
Figure 67. T1/J1 Mode Jitter Tolerance (N1 = N2 = 2fH) ............................................................................................................................................ 87
Figure 68. T1/J1 Mode Jitter Transfer (N1 = N2 = 2fH) ............................................................................................................................................... 87
Figure 69. Transmit Clock Select ................................................................................................................................................................................. 88
Figure 70. Line Loopback ............................................................................................................................................................................................ 90
Figure 71. Digital Loopback ......................................................................................................................................................................................... 91
Figure 72. Payload Loopback ...................................................................................................................................................................................... 92
Figure 73. Interrupt Service in E1 Mode HDLC Receiver ............................................................................................................................................ 99
Figure 74. Writing Data to E1 Mode THDLC FIFO .................................................................................................................................................... 100
Figure 75. Interrupt Service in E1 Mode HDLC Transmitter ...................................................................................................................................... 101
Figure 76. Polling Mode in E1 Mode HDLC Transmitter ............................................................................................................................................ 102
Figure 77. Writing Sequence of Indirect Register in E1 Mode ................................................................................................................................... 107
Figure 78. Reading Sequence of Indirect Register in E1 Mode ................................................................................................................................. 107
Figure 79. Interrupt Service in T1/J1 Mode HDLC Receiver ..................................................................................................................................... 115
Figure 80. Writing Data to T1/J1 Mode THDLC FIFO ................................................................................................................................................ 116
Figure 81. Interrupt Service in T1/J1 Mode HDLC Transmitter ................................................................................................................................. 117
Figure 82. Polling Mode in T1/J1 Mode HDLC Transmitter ....................................................................................................................................... 118
Figure 83. Writing Sequence of Indirect Register in T1/J1 Mode .............................................................................................................................. 122
Figure 84. Reading Sequence of Indirect Register in T1/J1 Mode ............................................................................................................................ 123
Figure 85. JTAG Architecture .................................................................................................................................................................................... 268
Figure 86. JTAG State Diagram ................................................................................................................................................................................ 272
Figure 87. Read Access Timing ................................................................................................................................................................................. 277
Figure 88. Write Access Timing ................................................................................................................................................................................. 278
Figure 89. Transmit Interface Timing (Transmit System Common Clock #B) ........................................................................................................... 279
Figure 90. Transmit Interface Timing (Line Transmit Clock) ...................................................................................................................................... 279
Figure 91. Receive Interface Timing (Receive System Common Clock) ................................................................................................................... 280
Figure 92. Receive Interface Timing (Receive System Clock) .................................................................................................................................. 280
Figure 93. Receive Line Interface Timing .................................................................................................................................................................. 281
Figure 94. Transmit Line Interface Timing ................................................................................................................................................................. 281
March 5, 2009
List of Figures
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