IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 68

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
3.13.1.1.1
clocked by TSCCKB. The active edge of TSCCKB used to sample the
each time slot is the first bit to be transmitted.
Slave mode, the special feature in this mode is that the multi-functional
pin TSFSn/TSSIGn is used as TSFSn to output a framing pulse to indi-
cate the first bit of each Basic Frame.
Functional Description
Table 28: Active Edge Selection of TSCCKB (in E1 Transmit Clock
Slave TSFS Enable Mode)
Note:
If the FE is not equal to the DE, the active edge decided by the FE is one clock edge
before the active edge decided by the DE.
The FE (b3, E1-018H) of the eight framers should be set to the same value to ensure
TSCFS for the eight framers is sampled on the same active edge.
In this mode (refer to Figure 37), the data on the system interface is
Figure 38 & Figure 39 show the functional timing examples. Bit 1 of
Besides all the common functions described in the Transmit Clock
TSCFS
TSFSn
TSDn
Transmit Clock Slave TSFS Enable Mode
Note: * TSCFS, TSD, TSFS are timed to TSCCKB
TSCCKA
TSCCKB
TSCFS *
TSD[1:8] *
TSFS[1:8] *
the Bit Determining the Active Edge of TSCCKB
TSFSRISE (b2, E1-002H)
DE (b4, E1-018H)
FE (b3, E1-018H)
Figure 37. Transmit Clock Slave TSFS Enable Mode
Transmit
Interface
System
TRANSMITTER
Generator
Frame
58
pulse on TSCFS and the data on TSDn and TSFSn is determined by the
following bits in the registers (refer to Table 28).
DPLL
FIFO
T1 / E1 / J1 OCTAL FRAMER
LRCK[1:8]
LTCK[1:8]
LTD[1:8]
March 5, 2009