IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 80

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
3.13.2.1
1.544 Mb/s. However, if the system clock rate is 2.048MHz, the data to
be transmitted should be converted into the same rate as the line side,
that is, to work in T1/J1 mode E1 rate. Thus the RATE[1:0] (b3~2, T1/J1-
005H) should be set to ‘01’. The conversion complies as follows: The
mon Clock B (TSCCKB) is provided by the system side. It is used as a
common timing clock for all eight framers. The speed of TSCCKB can
be 1.544MHz or 2.048MHz. When it is 2.048MHz, TSCCKB can be cho-
sen by the CMS (b5, T1/J1-015H) to be the same as the data (2.048Mb/
S), or double the data (4.096Mb/s). The CMS (b5, T1/J1-015H) of the
eight framers should be set to the same value. If the speed of TSCCKB
is double of the data, there will be two active edges in one bit duration. In
this case, the COFF (b4, T1/J1-015H) determines the active edge to
sample the signal on the TSDn and TSSIGn pins and the active edge to
update the pulse on the TSFSn pin; however, the pulse on TSCFS is
always sampled on its first active edge.
mon Clock A (TSCCKA) is provided by the system side. It is used as one
of the reference clocks for the transmit jitter attenuator DPLL for all eight
framers (refer to Chapter 3.20 Transmit Clock for details).
mon Frame Pulse (TSCFS) is used as a common framing signal to align
data streams for the eight framers. TSCFS is asserted on the request of
each F-bit, the first F-bit of every 12 SFs or every 24 ESFs, as indicated
by the TSCFSP (b1, T1/J1-005H). The valid polarity of TSCFS is config-
ured by the FPINV (b5, T1/J1-005H).
Clock Slave TSFS Enable Mode and Transmit Clock Slave External Sig-
naling Mode.
3.13.2.1.1
clocked by TSCCKB. The active edge of TSCCKB to sample the pulse
on TSCFS and the data on TSDn and TSFSn is determined by the fol-
lowing bits in the registers (refer to Table - 35).
Functional Description
2.048M
1.544M
bit/s
bit/s
In the Transmit Clock Slave mode, the bit rate on the TSDn pin is
In the Transmit Clock Slave mode, the Transmit Side System Com-
In the Transmit Clock Slave mode, the Transmit Side System Com-
In the Transmit Clock Slave mode, the Transmit Side System Com-
The Transmit Clock Slave Mode includes two sub-modes: Transmit
In this mode (refer to Figure 37), the data on the system interface is
Transmit Clock Slave Mode
discarded
Transmit Clock Slave TSFS Enable Mode
TS0
the last bit
F
CH1
TS1
CH2
TS2
Figure 53. E1 To T1/J1 Format Conversion
CH3
TS3
discarded
CH4
TS4
70
last bit of Frame N of the system side is the F-bit of Frame N in the
device. Then one byte of the system side is discarded after the previous
three bytes are converted into the device. This process repeats eight
times and the conversion of one frame is completed. Then the process
goes on (refer to Figure 53).
each channel is the first bit to be transmitted.
Slave mode, the special feature in this mode is that the multi-functional
pin TSFSn/TSSIGn is used as TSFSn to output a framing pulse to indi-
cate every F-bit.
Table 35: Active Edge Selection of TSCCKB (in T1/J1 Transmit
Clock Slave TSFS Enable Mode)
Note:
The TSCCKBFALL (b3, T1/J1-004H) of the eight framers should be set to the same
value to ensure TSCFS for the eight framers is sampled on the same active edge.
CH5
TS5
Figure 54 to Figure 56 show the functional timing examples. Bit 1 of
Besides all the common functions described in the Transmit Clock
TSCFS
TSFS
TSD
TS6
the Bit Determining the Active Edge of TSCCKB
TSCCKBFALL (b3, T1/J1-004H)
TSFSRISE (b5, T1/J1-004H)
T1 / E1 / J1 OCTAL FRAMER
CH24
TS31
discarded
F
TS0
CH1
the last bit
March 5, 2009
TS2