IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 55

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
3.11.2.1
1.544Mb/s. However, if the system clock rate is 2.048MHz, the received
data stream (1.544 Mb/s) should be converted to the same rate as the
system side, that is, to work in T1/J1 mode E1 rate. Thus, the
RSCCK2M (b4, T1/J1-001H) and the RSCCK8M (b3, T1/J1-001H)
should be set to logic 1 and 0 respectively. The conversion complies as
mon Clock (RSCCK) is provided by the system side. It is used as a com-
mon timing clock for all eight framers. The speed of RSCCK can be
1.544MHz or 2.048MHz. When it is 2.048MHz, RSCCK can be chosen
by the CMS (b4, T1/J1-078H) to be the same as the received data
(2.048Mb/s), or double the received data (4.096 Mb/s). The CMS (b4,
T1/J1-078H) of the eight framers should be set to the same value. If the
speed of RSCCK is double the received data stream, there will be two
active edges in one bit duration. In this case, the RSD_RSCFS_EDGE
(b5, T1/J1-078H) determines the active edge to update the signal on the
RSDn, RSSIGn and RSFSn pins; however, the pulse on RSCFS is
always sampled on its first active edge.
mon Frame Pulse (RSCFS) is used as a common framing signal to align
the data stream for all eight framers. RSCFS asserts on each F-bit and
its valid polarity is configured by the FPINV (b6, T1/J1-078H).
of SF/ESF, every second F-bit, the first F-bit of every 12 frames (in SF
format) or every 24 frames (in ESF format). All the indications are
selected by the RSFSP (b2, T1/J1-001H) and ALTIFP (b1, T1/J1-001H).
The valid polarity of RSFSn is configured by the FPINV (b6, T1/J1-
078H).
Clock Slave RSCK Reference Mode and Receive Clock Slave External
Signaling Mode. Note that if the receive system interface is configured to
operate in T1/J1 mode E1 rate, framer 1, 3, 5, 7 must be configured in
the same sub-mode and framer 2, 4, 6, 8 must be configured in the
same sub-mode.
3.11.2.1.1
clocked by RSCCK. The active edge of RSCCK to sample the data on
Functional Description
1.544M bit/s
2.048M bit/s
In the Receive Clock Slave Mode, the bit rate on the RSDn pin is
In the Receive Clock Slave Mode, the Receive Side System Com-
In the Receive Clock Slave Mode, the Receive Side System Com-
In the Receive Clock Slave Mode, RSFSn can indicate each F-bit
The Receive Clock Slave Mode includes two sub-modes: Receive
In this mode (refer to Figure 9), the data on the system interface is
Receive Clock Slave Mode
Receive Clock Slave RSCK Reference Mode
inserted
TS0
the 8th bit
F
CH1
TS1
CH2
TS2
Figure 24. T1/J1 To E1 Format Conversion
CH3
TS3
inserted
CH4
TS4
45
follows: One dummy byte is inserted in the system side before 3 bytes of
Frame N from the device are converted. This process repeats 8 times
and the conversion of Frame N of 1.544M bit/s data rate to 2.048M bit/s
data rate is completed. However, the F-bit of Frame N of the 1.544M bit/
s data rate is inserted as the 8th bit of the N of the 2.048M bit/s data rate
(refer to Figure 24).
the RSCFS pin or to update the data on the RSDn and RSFSn pins is
determined by the following bits in the registers (refer to Table 22).
Table 22: Active Edge Selection of RSCCK (in T1/J1 Receive Clock
Slave RSCK Reference Mode)
each channel is the first bit to be output.
Slave mode, the special feature in this mode is that the multi-functional
pin RSCKn/RSSIGn is used as RSCKn to output a reference clock.
RSCKn can be chosen by the RSCKSEL (b5, T1/J1-001H) to output a
jitter attenuated 1.544MHz (i.e., smoothed LRCKn) or 8KHz clock
(smoothed LRCKn divided by 193).
Note:
The RSCFSFALL (b1, T1/J1-003H) of the eight framers should be set to the same value
to ensure RSCFS for the eight framers is sampled on the same active edge.
It is a special case when the CMS (b4, T1/J1-078H) is logic 1 and the RSCFSFALL (b1,
T1/J1-003H) is not equal to RSCCKRISE (b0, T1/J1-003H). The RSD_RSCFS_EDGE
(b5, T1/J1-078H) is invalid and the signals on the RSDn and the RSFSn pins are updated
on the first active edge of RSCCK.
CH5
TS5
Figure 25 to Figure 27 show the functional timing examples. Bit 1 of
Besides all the common functions described in the Receive Clock
RSCFS
RSFSn
RSDn
TS6
the Bit Determining the Active Edge of RSCCK
RSCCKRISE (b0, T1/J1-003H)
RSCFSFALL (b1, T1/J1-003H)
CH24
TS31
T1 / E1 / J1 OCTAL FRAMER
inserted
F
TS0
CH1
the 8th bit
March 5, 2009
TS1