IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 232

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
T1 / J1 TRSI Time Slot Offset (014H, 094H, 114H, 194H, 214H, 294H, 314H, 394H)
on the TSCFS pin and the start of the corresponding frame transmitted on TSDn & TSSIGn.
the TSCFS pin and the start of the corresponding frame transmitted on TSDn.
of the corresponding frame transmitted on MTSD.
T1 / J1 TRSI Bit Offset (015H, 095H, 115H, 195H, 215H, 295H, 315H, 395H)
MTBS:
CMS:
COFF:
BOFF[2:0]:
TSCFS pin and the start of the SF/ESF transmitted on TSDn & TSSIGn.
TSCFS pin and the start of the SF/ESF transmitted on TSDn.
SF/ESF transmitted on MTSD & MTSSIG.
Programming Information
Bit Name
Bit Name
Default
Bit No.
Default
Bit No.
Type
In T1/J1 Transmit Clock Slave External Signaling mode E1 rate, the content in the TSOFF[6:0] determines the channel offset between the signal
In T1/J1 Transmit Clock Slave TSFS Enabled mode E1 rate, the content in the TSOFF[6:0] determine the channel offset between the signal on
In Transmit Multiplexed mode, the content in the TSOFF[6:0] determine the channel offset between the signal on the MTSCFS pin and the start
Except for the above three modes, the channel offset is disabled. Thus, the TSOFF[6:0] must be logic 0.
These bits define a binary number. The offset can be set from 0 to 127 channels.
Valid in Transmit Multiplexed mode.
= 0: Data of the current channel is taken from the first multiplexed bus (MTSD[1], MTSSIG[1]).
= 1: Data of the current channel is taken from the second multiplexed bus (MTSD[2], MTSSIG[2]).
= 0: The clock rate of TSCCKB/MTSCCKB is the same as that of the backplane.
= 1: The clock rate of TSCCKB/MTSCCKB is double that of the backplane.
The CMS of the eight framers should be set to the same value.
Valid when the CMS (b5, T1/J1-015H) is logic 1.
= 0: The first active edge of TSCCKB/MTSCCKB is used to sample / update the data.
= 1: The second active edge of TSCCKB/MTSCCKB is used to sample / update the data.
In Transmit Clock Multiplexed mode, the COFF of the eight framers should be set to the same value.
In T1/J1 Transmit Clock Slave External Signaling mode E1 rate, the content in the BOFF[2:0] determines the bit offset between the signal on the
In T1/J1 Transmit Clock Slave TSFS Enabled mode E1 rate, the content in the BOFF[2:0] determines the bit offset between the signal on the
In Transmit Multiplexed mode, the content in the BOFF[2:0] determines the bit offset between the signal on the MTSCFS pin and the start of the
Except for the above three modes, the bit offset is disabled. Thus, the BOFF[2:0] must be logic 0.
These bits define a binary number. Refer to the Functional Description for details.
Type
Reserved
Reserved
7
7
TSOFF[6]
MTBS
R/W
R/W
6
0
6
0
TSOFF[5]
R/W
CMS
R/W
5
0
5
0
TSOFF[4]
COFF
R/W
R/W
4
0
4
0
222
TSOFF[3]
Reserved
R/W
3
0
3
TSOFF[2]
BOFF[2]
R/W
R/W
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
TSOFF[1]
BOFF[1]
R/W
R/W
1
0
1
0
March 5, 2009
TSOFF[0]
BOFF[0]
R/W
R/W
0
0
0
0