IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 151

IC FRAMER T1/J1/E1 8CH 128-PQFP

IDT82V2108PXG8

Manufacturer Part Number
IDT82V2108PXG8
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82V2108PXG8

Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V2108PXG8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT82V2108PXG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT82V2108
E1 Clock Monitor (00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH)
sponding bit in this register is set to ‘1’, and this bit remains to be ‘1’ until this register is read. After a read operation on this register, all the bits in this
register will be cleared to ‘0’. A lack of transitions of the monitored clock will be indicated by ‘0’ in the corresponding bit, which means that the clock
fails. This register should be read periodically to detect clock failures.
XCK:
TSCCKB:
TSCCKA:
RSCCK:
LRCK:
Programming Information
Bit Name
Default
Bit No.
Type
This register provides activity monitoring on the IDT82V2108 clocks. When a monitored clock signal makes a low to high transition, the corre-
= 0: After the bit is read.
= 1: A low to high transition occurs on XCK.
= 0: After the bit is read.
= 1: A low to high transition occurs on TSCCKB.
= 0: After the bit is read.
= 1: A low to high transition occurs on TSCCKA.
= 0: After the bit is read.
= 1: A low to high transition occurs on RSCCK.
= 0: After the bit is read.
= 1: A low to high transition occurs on LRCK.
7
Reserved
6
5
XCK
R
X
4
141
TSCCKB
R
X
3
TSCCKA
R
2
X
T1 / E1 / J1 OCTAL FRAMER
RSCCK
R
X
1
March 5, 2009
LRCK
R
X
0

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