IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 234

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
T1 / J1 TJAT Configuration (01BH, 09BH, 11BH, 19BH, 21BH, 29BH, 31BH, 39BH)
CENT:
UNDE:
OVRE:
LIMIT:
the read pointer is 1 UI away from the FIFO being empty or full. This limitation of jitter attenuation ensures that no data is lost during high phase shift
conditions.
T1 / J1 ELSB Interrupt Enable / Status (01DH, 09DH, 11DH, 19DH, 21DH, 29DH, 31DH, 39DH)
SLIPE:
SLIPD:
SLIPI:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
The CENT allows the TJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full.
= 0: Disable the self-center. Data passes through uncorrupted when the FIFO is empty or full.
= 1: Enable the FIFO to self-center its read pointer when the FIFO is 4 UI away from being empty or full.
A positive transition in this bit will execute a self-center action immediately.
This bit decides whether to generate an interrupt when the TJAT FIFO is under-run.
= 0: No interrupt is generated when the TJAT FIFO is under-run.
= 1: An interrupt on the INT pin is generated when the TJAT FIFO is under-run.
This bit decides whether to generate an interrupt when the TJAT FIFO is overwritten.
= 0: No interrupt is generated when the TJAT FIFO is overwritten.
= 1: An interrupt on the INT pin is generated when the TJAT FIFO is overwritten.
= 0: Disable the limitation of the jitter attenuation.
= 1: Enable the DPLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the output smoothed clock when
Type
= 0: Disable the interrupt on the INT pin when a slip occurs.
= 1: Enable the interrupt on the INT pin when a slip occurs.
This bit is valid when the SLIPI is logic 1.
= 0: The latest slip is due to the Elastic Store Buffer being empty; a frame was duplicated.
= 1: The latest slip is due to the Elastic Store Buffer being full; a frame was deleted.
= 0: No slip occurs.
= 1: A slip occurs.
This bit is cleared to ‘0’ after the bit is read.
7
7
Reserved
6
6
Reserved
5
5
CENT
R/W
4
0
4
224
UNDE
R/W
3
0
3
OVRE
SLIPE
R/W
R/W
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
Reserved
SLIPD
1
R
X
1
March 5, 2009
LIMIT
SLIPI
R/W
R
0
1
0
X