IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 223

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
T1 / J1 Transmit Side System Interface Options (005H, 085H, 105H, 185H, 205H, 285H, 305H, 385H)
EMODE[1:0]:
FPINV:
ABXXEN:
the ‘A’ bit will be inserted to the signaling bit of Frame 6 and 18, and the ‘B’ bit will be inserted to the signaling bit of Frame 12 and 24.
RATE[1:0]:
plane bit rate, the multiplexed bus will be enabled for the chip. When the RATE[1:0] selects the 2.048 Mbit/s or 8.192 Mbit/s, the EMODE[1] (b7, T1/J1-
005H) must be set to ‘1’ (i.e., in Transmit Clock Slave mode).
TSCFSP:
Programming Information
Bit Name
Default
Bit No.
Type
In Transmit Multiplexed mode, these bits must be set to ‘11’.
= 0: The positive pulse on the TSCFS/MTSCFS pin is valid.
= 1: The negative pulse on the TSCFS/MTSCFS pin is valid.
This bit of the eight framers should be set to the same value.
This bit is valid only in T1 ESF mode.
= 0: The valid signaling on the TSSIGn/MTSSIG pin is in the lower four nibble of each channel (i.e. XXXXABCD).
= 1: The valid signaling on the TSSIGn/MTSSIG pin is in the upper two-bit positions of the lower nibble of each channel (i.e. XXXXABXX). Thus,
These bits determine the bit rate of the transmit data stream on the backplane. Note that if any of the eight framers selects the 8.192 Mbit/s back-
= 0: Indicate that the signal on the TSCFS pin asserts on each F-bit.
= 1: Indicate that the signal on the TSCFS pin asserts on the first F-bit of every 12 SFs or every 24 ESFs.
This bit of the eight framers should be set to the same value.
EMODE[1]
R/W
7
1
EMODE[0]
R/W
6
1
EMODE[1:0]
0 0
0 1
1 0
1 1
RATE[1:0]
FPINV
R/W
0 0
0 1
1 0
1 1
5
0
Transmit Clock Slave External Signaling mode
ABXXEN
Transmit Clock Slave TSFS Enable mode
R/W
Operation Mode In Transmitter Path
4
0
213
Transmit Clock Master mode
Reserved
Backplane Rate
RATE[1]
1.544M bit/s
2.048M bit/s
8.192M bit/s
R/W
Reserved
3
0
RATE[0]
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
TSCFSP
R/W
1
0
March 5, 2009
Reserved
0