IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 230

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
UNF_GEN:
UNF_DET:
T1 / J1 RJAT Interrupt Status (010H, 090H, 110H, 190H, 210H, 290H, 310H, 390H)
OVRI:
UNDI:
T1 / J1 RJAT Reference Clock Divisor (N1) Control (011H, 091H, 111H, 191H, 211H, 291H, 311H, 391H)
input reference clock and the frequency applied to the phase discriminator input.
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
= 0: Which channels of the selected path will be replaced by the PRGD pattern is specified by TPLC or RPLC.
= 1: All 24 channels and the F-bit of the selected path will be replaced by the PRGD pattern.
= 0: Which channels of the selected path will be detected by PRGD pattern is specified by TPLC or RPLC.
= 1: All 24 channels and the F-bit of the selected path will be detected by PRGD pattern.
If data is still attempted to write into the FIFO when the FIFO is already full, the overwritten event will occur.
= 0: The RJAT FIFO is not overwritten.
= 1: The RJAT FIFO is overwritten.
This bit is cleared to ‘0’ when it is read.
If data is still attempted to read from the FIFO when the FIFO is already empty, the under-run event will occur.
= 0: The RJAT FIFO is not under-run.
= 1: The RJAT FIFO is under-run.
This bit is cleared to ‘0’ when it is read.
These bits define a binary number. The (N1[7:0] + 1) is the divisor of the input reference clock, which is the ratio between the frequency of the
Writing to this register will reset the DPLL in the RJAT.
Type
N1[7]
R/W
7
0
7
N1[6]
R/W
6
0
6
N1[5]
R/W
5
1
5
Reserved
N1[4]
R/W
4
0
4
220
N1[3]
R/W
3
3
1
N1[2]
R/W
2
2
1
T1 / E1 / J1 OCTAL FRAMER
OVRI
N1[1]
R/W
R
X
1
1
1
March 5, 2009
UNDI
N1[0]
R/W
R
X
0
0
1