IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 179

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
E1 FRMP CRC Error Counter-MSB / Time Slot 16 Extra Bits (03AH, 0BAH, 13AH, 1BAH, 23AH, 2BAH, 33AH, 3BAH)
OVR:
one second interval.
NEWDATA:
X[0:2], Y:
Signaling Multi-Frame. They are updated on the generation of the IFPI interrupt on NFAS frames. Note that these bits are not updated when the
received data stream is out of Basic Frame. The position of the X[2:0] and Y bit is shown in the following table:
CRCERR[9:8]:
MSB.
Programming Information
Bit Name
Frame 0
Default
Bit No.
Type
Overwritten means that the data is still written into the CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) without the data being read in the latest
= 0: The CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) are not overwritten.
= 1: The CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) are overwritten.
This bit is clear to ‘0’ after it is read.
= 0: The value in the CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) has not been updated with new value.
= 1: The value in the CRCERR[9:0] (b1~0, E1-03AH & b7~0, E1-039H) has been updated with new value.
This bit is clear to ‘0’ after it is read. This bit can be polled to determine the 1 second timing boundary used by the Frame Processor.
Directly reflect the content in the Extra bits (X[0:2]) and the Remote Signaling Multi-Frame Alarm bit (Y) in Frame0 of TS16 of the latest received
The CRCERR[9:8], together with the CRCERR[7:0], represent the number of the CRC errors and update every second. The CRCERR[9] is the
OVR
R
7
0
0
0
NEWDATA
R
6
0
1
0
X[0]
R
X
5
2
0
Y
R
X
4
3
0
169
Eight Bits in TS16
X[1]
X[0]
R
X
3
4
X[2]
R
2
X
5
Y
T1 / E1 / J1 OCTAL FRAMER
CRCERR[9]
X[1]
R
X
1
6
March 5, 2009
CRCERR[8]
X[2]
R
X
0
7