IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 225

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
T1 / J1 Transmit Timing Options (007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H)
TJATREF_SEL[2:0]:
LTCK_SEL[2:0]:
T1 / J1 Interrupt Source #1 (008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H)
indication. To clear the interrupt indication on the INT pin, the corresponding interrupt status register must be read.
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
The TJATREF_SEL[2:0] select the input reference clock for the TJAT DPLL.
Bits in this register indicate which function block introduced an interrupt signal on the INT pin. Reading this register does not clear the interrupt
PMON
R/W
7
0
7
Reserved
IBCD
R/W
6
0
6
LTCK_SEL[2:0]
others
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
TJATREF_SEL[2:0]
TJATREF_SEL[2] TJATREF_SEL[1] TJATREF_SEL[0]
FRMP
R/W
R/W
others
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
5
0
5
1
A smoothed clock output from the TJAT DPLL
PRGD
R/W
R/W
4
0
215
4
0
Line Transmit Clock
Input Reference Clock
TSCCKA / 8
TSCCKB
TSCCKA
XCK / 24
TSCCKA / 8
LRCK
TSCCKB
TSCCKA
XCK / 24
TSCCKB
ELSB
R/W
LRCK
3
0
R/W
3
0
LTCK_SEL[2]
RHDLC#1
R/W
R/W
2
0
2
1
T1 / E1 / J1 OCTAL FRAMER
LTCK_SEL[1]
RBOM
R/W
R/W
1
0
1
0
March 5, 2009
LTCK_SEL[0]
ALMD
R/W
R/W
0
1
0
0