IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 150

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
E1 Interrupt ID (00BH)
duced the interrupt, the corresponding bit in the INT[8:1] will be ‘1’.
E1 Pattern Generator / Detector Positioning / Control (00CH)
This register selects which framer will use the PRGD and how the PRGD will be used.
PRGDSEL[2:0]:
RXPATGEN:
UNF_GEN:
UNF_DET:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
This register indicates which one of the eight framers introduced the interrupt INT pin to be logic low. When any one of the eight framers intro-
The IDT82V2108 has only one PRBS Generator/Detector (PRGD) shared by all eight framers. At one time, only one framer can use this PRGD.
PRGDSEL[2:0] select one of the eight framers to be tested by the PRGD block.
= 0: The pattern in PRGD is generated in the transmit path and is detected in the receive path.
= 1: The pattern in PRGD is generated in the receive path and is detected in the transmit path.
= 0: Which time slots of the selected path will be replaced by the PRGD pattern is specified in TPLC or RPLC.
= 1: All 32 time slots of the selected path will be replaced by the PRGD pattern.
= 0: Which time slots of the selected path will be detected by PRGD pattern is specified in TPLC or RPLC.
= 1: All 32 time slots of the selected path will be detected by PRGD pattern.
PRGDSEL[2]
INT[8]
R/W
R
X
7
7
0
PRGDSEL[1]
INT[7]
R/W
R
6
X
6
0
PRGDSEL[0]
PRGDSEL[2:0]
INT[6]
R/W
R
X
5
5
0
000
001
010
011
100
101
110
111
INT[5]
R
X
4
4
140
Reserved
Selected Framer
Framer 1
Framer 2
Framer 3
Framer 4
Framer 5
Framer 6
Framer 7
Framer 8
INT[4]
R
X
3
3
RXPATGEN
INT[3]
R/W
R
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
UNF_GEN
INT[2]
R/W
R
1
0
1
0
March 5, 2009
UNF_DET
INT[1]
R/W
R
0
0
0
0