IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 122

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
Table 53: Various Operation Modes in Transmit Path for Reference (Continued)
Operation
Transmit Clock
Transmit Multi-
Master Mode
plexed Mode
Mode
Register
0C4H
1C4H
2C4H
3C4H
004H
005H
044H
007H
004H
084H
104H
184H
204H
284H
304H
384H
005H
085H
105H
185H
205H
285H
305H
385H
014H
094H
114H
194H
214H
294H
314H
394H
015H
095H
115H
195H
215H
295H
315H
395H
044H
144H
244H
344H
1
Value (from Bit7 to Bit0)
00000110
01000000
00000000
00100100
00001000
00001000
00001000
00001000
00001000
00001000
00001000
00001000
00000000
00000000
00000001
00000001
00000010
00000010
00000011
00000011
00000000
01000000
00000000
01000000
00000000
01000000
00000000
01000000
00010000
00010000
00010000
00010000
00010000
00010000
00010000
00010000
11001100
11001100
11001100
11001100
11001100
11001100
11001100
11001100
The data on the TSFSn pin is updated on the rising edge of LTCK. The data on the TSDn pin is sam-
pled on the falling edge of LTCK.
In the Transmit Clock Master Full T1/J1 mode. The backplane rate is 1.544 Mbit/s.
XCK/24 is selected as TJAT input reference clock and Line Transmit Clock
In the Transmit Multiplexed mode. The backplane rate is 8.192 Mbit/s.
TSOFF[6:0] = 0. The time slot offset is 0.
TSOFF[6:0] = 1. The time slot offset is 1.
TSOFF[6:0] = 2. The time slot offset is 2.
TSOFF[6:0] = 3. The time slot offset is 3.
The data stream is taken from multiplexed bus 1.
The data stream is taken from multiplexed bus 2.
The data stream is taken from multiplexed bus 2.
The data stream is taken from multiplexed bus 1.
The data stream is taken from multiplexed bus 2.
The data stream is taken from multiplexed bus 1.
The data stream is taken from multiplexed bus 2.
The Frame Generator is set in the SF format.
The data on the TSDn, TSSIGn and TSCFS pins is sampled on the falling edge of TSCCKB.
The data stream is taken from multiplexed bus 1.
The Frame Generator is set in the ESF format.
112
Description
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T1 / E1 / J1 OCTAL FRAMER
March 5, 2009