IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 220

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
T1 / J1 Backplane Parity Configuration / Status (002H, 082H, 102H, 182H, 202H, 282H, 302H, 382H)
TPTYP:
the F-bit position when the number of ones in the previous SF/ESF is odd.
F-bit position when the number of ones in the previous SF/ESF is even.
TPRTYE:
SIG pin.
SIG pin.
TSDI:
TSSIGI:
PTY_EXTD:
MRSSIG pins.
MRSSIG pins.
RPTYP:
replaced in the F-bit when the number of ones in the previous SF/ESF is odd.
replaced in the F-bit when the number of ones in the previous SF/ESF is even.
RPRTYE:
Programming Information
Bit Name
Default
Bit No.
Type
= 0: Even parity check is employed in the F-bit input from the TSDn/MTSD and TSSIGn/MTSSIG pins, which means a logic one is expected in
= 1: Odd parity check is employed in the F-bit input from the TSDn/MTSD and TSSIGn/MTSSIG pins, which means a logic one is expected in the
This bit is invalid in Receive Clock Master Fractional T1/J1 mode.
= 0: Disable the interrupt on the INT pin when a parity error is detected on the TSDn/MTSD pin or a parity error is detected on the TSSIGn/MTS-
= 1: Enable the interrupt on the INT pin when a parity error is detected on the TSDn/MTSD pin or a parity error is detected on the TSSIGn/MTS-
= 0: Indicate that no parity error is detected on the TSDn/MTSD pin.
= 1: Indicate that a parity error is detected on the TSDn/MTSD pin.
This bit is cleared to ‘0’ after the bit is read.
= 0: Indicate that no parity error is detected on the TSSIGn/MTSSIG pin.
= 1: Indicate that a parity error is detected on the TSSIGn/MTSSIG pin.
This bit is cleared to ‘0’ after the bit is read.
= 0: The parity is calculated over the previous SF/ESF, excluding the F-bit on the TSDn/MTSD, TSSIGn/MTSSIG, RSDn/MRSD and RSSIGn/
= 1: The parity is calculated over the previous SF/ESF, including the F-bit on the TSDn/MTSD, TSSIGn/MTSSIG, RSDn/MRSD and RSSIGn/
This bit is invalid in Receive Clock Master Fractional T1/J1 mode and valid when the RPRTYE is ‘1’.
= 0: Even parity check is employed in the F-bit output on the RSDn/MRSD and RSSIGn/MRSSIG pins, which means a logic one should be
= 1: Odd parity check is employed in the F-bit output on the RSDn/MRSD and RSSIGn/MRSSIG pins, which means a logic one should be
This bit is invalid in Receive Clock Master Fractional T1/J1 mode.
= 0: Disable the parity on the RSDn/MRSD and RSSIGn/MRSSIG pins.
= 1: Enable the parity on the RSDn/MRSD and RSSIGn/MRSSIG pins.
TPTYP
R/W
7
0
TPRTYE
R/W
6
0
TSDI
R
X
5
TSSIGI
R
X
4
210
PTY_EXTD
R/W
3
0
Reserved
2
T1 / E1 / J1 OCTAL FRAMER
RPTYP
R/W
1
0
March 5, 2009
RPRTYE
R/W
0
0