IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 144

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
isters on per time slot basis. This bit only has effect in the Receive Clock Slave mode, and it affects the corresponding time slot of multiplexed bus
MRSD when multiplexed bus operation is enabled.
RXMTKC:
ters and the RPLC Signaling Trunk Conditioning Registers. This bit affects the corresponding time slot of MRSD and MRSSIG if the multiplexed back-
plane is enabled.
Control Byte registers in the RPLC.
RSSIGn of all time slots is replaced with the data contained in the Signaling Trunk Conditioning registers. To enable this function, the PCCE (b0, E1-
05CH) of the RPLC must be set to logic 1.
E1 Transmit Path Configuration (002H, 082H, 102H, 182H, 202H, 282H, 302H, 382H)
FIFOBYP:
TAISEN:
PATHCRC:
Frame format, and the IDT82V2108 is going to change some bits in the data stream, this bit decides whether to replace the original CRC-4 bits with re-
calculated CRC-4 bits or just modify the original CRC-4 bits according to the contribution caused by changing bits in the data stream. This bit only
takes effect when the FPTYP (b1, E1-019H) is set to ‘1’ and one of the INDIS (b1, E1-040H) or FDIS (b3, E1-045H) is set to ‘1’.
errors in upstream can not be detected by the downstream.
be transmitted to the downstream transparently, and the downstream machine can detect it.
TSFSRISE:
LTCKRISE:
Programming Information
Bit Name
Default
Bit No.
Type
= 0: ELSB Idle Code Substitution is disabled.
= 1: Data in all time slots on RSDn will be replaced by the contents in ELSB Idle Code Register during out of Basic frame.
This bit decides how to substitute the received data stream on RSDn and RSSIGn with the contents in the RPLC Data Trunk Conditioning Regis-
= 0: The data and the signaling are substituted on a per-timeslot basis in accordance with the control bits contained in the per-timeslot Payload
= 1: The data on RSDn of all time slots is replaced with the data contained in the Data Trunk Conditioning registers in RPLC, and the signaling on
This bit decides whether the transmit data should pass through or bypass the Transmit Jitter Attenuation FIFO.
= 0: The transmit data pass through the TJAT FIFO.
= 1: The TJAT FIFO is bypassed. The delay is reduced by typically 24 bits.
This bit enables the line interface to generate an un-framed all-ones Alarm Indication Signal on the LTDn pin.
= 0: normal operation.
= 1: LTDn transmits all ‘One’s.
This bit allows upstream bit errors to be transmitted to the downstream transparently. When the data stream on TSDn is already in the CRC Multi-
= 0: A new re-calculated CRC-4 value will overwrite the incoming CRC-4 word. As the new CRC-4 value is transmitted to downstream, the bit
= 1: The incoming CRC-4 value is modified to just reflect the bit changes made by the IDT82V2108. If there is any bit error in the upstream, it will
This bit chooses the active edge of TSCCKB to update the Transmit Frame Pulse on the TSFSn pin.
= 0: the signal on TSFSn is updated on the falling edge of TSCCKB.
= 1: the signal on TSFSn is updated on the rising edge of TSCCKB.
This bit chooses the active edge of LTCKn to update the data on LTDn.
= 0: the data on LTDn pin is updated on the falling edge of LTCKn.
= 1: the data on LTDn pin is updated on the rising edge of LTCKn.
FIFOBYP
R/W
7
0
TAISEN
R/W
6
0
Reserved
5
PATHCRC
R/W
4
0
134
Reserved
3
TSFSRISE
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
Reserved
1
March 5, 2009
LTCKRISE
R/W
0
0