IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 67

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
3.13
to the chip. The input data to the eight framers can be aligned with each
other or inputted independently. The timing clocks and framing pulses
can be provided by the system back-plane common to eight framers or
provided for eight framers individually. The Transmit System Interface
supports various configurations to meet various requirements in different
applications.
3.13.1
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
TSDn pin is used to input the data to each framer at a bit rate of 2.048
Mb/s. While in the Multiplexed Mode, the data input to the eight framers
is byte-interleaved from two high speed data streams and inputs on the
MTSD1 and MTSD2 pins at a bit rate of 8.192 Mb/s.
on the TSDn pin is provided by the system side and shared by all eight
framers, the Transmit System Interface should be set in Transmit Clock
Slave mode. If the timing signal for clocking data on each TSDn pin is
3.13.1.1
mon Clock B (TSCCKB) is provided by the system side. It is used as a
common timing clock for all eight framers. The speed of TSCCKB can
be chosen by the CMS (b2, E1-018H) to be the same as the data to be
transmitted (2.048MHz), or twice the data (4.096MHz). The CMS (b2,
E1-018H) of the eight framers should be set to the same value. If the
speed of TSCCKB is twice the data to be transmitted, there will be two
active edges in one bit time. In this case, the COFF (b4, E1-01CH)
determines the active edge to sample the signal on the TSDn and
TSSIGn pins and the active edge to update the pulse on the TSFSn pin;
however, the pulse on TSCFS is always sampled on its first active edge.
mon Clock A (TSCCKA) is provided by the system side. It is used as one
Functional Description
Table 26: E1 Mode Transmit System Interface in Different Operation Modes
Table 27: Operation Mode Selection in E1 Transmit Path
11(All the eight framers should be set)
Non-Multiplexed
In E1 mode, the Transmit System Interface can be set in Non-multi-
In the Non-multiplexed Mode, if the timing signal for clocking data
In the Transmit Clock Slave mode, the Transmit Side System Com-
In the Transmit Clock Slave mode, the Transmit Side System Com-
RATE[1:0] (b1~0, E1-018H)
Mode
The Transmit System Interface determines how to input the data
TRANSMIT SYSTEM INTERFACE (TRSI)
E1 MODE
Transmit Clock Slave Mode
01
Clock Slave Mode
Multiplexed Mode
Operation Mode
Clock Master Mode
External Signaling
TSCKSLV (b5, E1-018H)
TSFS Enable
1
0
1
Data Pin
MTSD
TSDn
TSDn
TSDn
TSSIG_EN (b6, E1-003H)
57
0
1
1
-
MTSCCKB
provided from each line side (processed timing signal), the Transmit
System Interface should be set in Transmit Clock Master mode.
provided by the system side for the eight framers, the Transmit System
Interface should be set in Transmit Clock Slave mode. If there is no com-
mon framing pulse, the Transmit System Interface should be set in
Transmit Clock Master mode.
TSSIGn is used to output the framing indication pulse, the Transmit Sys-
tem Interface is in Transmit Clock Slave TSFS Enable mode. If TSFSn/
TSSIGn is used to input the signaling bits to be inserted, the Transmit
System Interface is in Transmit Clock Slave External Signaling mode.
TSSIGn is used as TSFSn to input the framing indication pulse.
operation modes. To set the transmit system interface of each framer
into various operation modes, the registers must be configured as
Table 27.
of the reference clocks for the transmit jitter attenuator DPLL for all eight
framers (refer to Chapter 3.20 Transmit Clock for details).
mon Frame Pulse (TSCFS) is used as a common framing signal to align
the data streams for the eight framers. TSCFS is asserted on each
Basic Frame or Multi-Frame indicated by the FPTYP (b1, E1-019H). The
valid polarity is configured by the FPINV (b3, E1-019H).
2.048Mb/s.
Clock Slave TSFS Enable Mode and Transmit Clock Slave External Sig-
naling Mode.
Clock Pin
TSCCKB
TSCCKB
LTCKn
In the Non-multiplexed Mode, if there is a common framing pulse
In the Transmit Clock Master mode, the multi-function pin TSFSn/
Table 26 summarizes the transmit system interface in different
In the Transmit Clock Slave mode, the Transmit Side System Com-
In the Transmit Clock Slave mode, the bit rate on the TSDn pin is
The Transmit Clock Slave Mode includes two sub-modes: Transmit
In the Transmit Clock Slave mode, if the multi-function pin TSFSn/
TSCFS & TSFSn
Framing Pin
MTSCFS
TSCFS
TSFSn
Transmit Clock Slave External Signaling
Transmit Clock Slave TSFS Enable
Transmit Clock Master
Transmit Multiplexed
Operation Mode
Signaling Pin
MTSSIG
TSSIGn
T1 / E1 / J1 OCTAL FRAMER
No
No
Reference Clock Pin
TSCCKA & TSCCKB
March 5, 2009
TSCCKA
TSCCKA
TSCCKA