IDT82V2108PXG8 IDT, Integrated Device Technology Inc, IDT82V2108PXG8 Datasheet - Page 61

• Manufacturer Part Number: IDT82V2108PXG8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG8

IDT82V2108
3.11.2.2.2
Master mode, the special feature in this mode (refer to Figure 17) is that
RSCKn is a gapped 1.544MHz clock (no clock signal during the selected
channel).
T1/J1-RPLC-indirect registers - 01~18H) in Receive Payload Control are
Functional Description
Besides all the common functions described in the Receive Clock
RSCKn is gapped during those channels with their EXTRACT (b2,
RSCKn
RSDn
RSCKn
RSFSn
RSDn
RSFSn
When the RSCKRISE (b3, T1/J1-003H) is logic 0:
When the RSCKRISE (b3, T1/J1-003H) is logic 1:
Figure 32. T1/J1 Receive Clock Master Fractional T1/J1 Mode - Functional Timing Example
Receive Clock Master Fractional T1/J1 Mode
4
4
CH24
CH24
5
5
RSCK is 1.544M. In this example, RSCK is supposed to be held in inactive state during CH2.
6
6
7
7
8
8
X
X
1
1
2
2
3
3
CH1
CH1
4
4
5
5
51
6
6
logic 0, and clocks out during those channels with their EXTRACT (b2,
T1/J1-RPLC-indirect registers - 01~18H) are logic 1. The data in the cor-
responding gapped channel is a don't care condition.
channel is the first bit to be output.
7
7
Figure 32 shows the functional timing examples. Bit 1 of each
8
8
Don't Care
Don't Care
T1 / E1 / J1 OCTAL FRAMER
1
1
March 5, 2009
2
2