SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet
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SAF1761BE/V1,557 Summary of contents
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SAF1761 Hi-Speed Universal Serial Bus On-The-Go controller Rev. 01 — 18 November 2009 1. General description The SAF1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with advanced NXP slave host controller and the peripheral controller. ...
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... NXP Semiconductors I Slave DMA implementation on CPU interface to reduce the host systems CPU load I Separate IRQ, DREQ and DACK lines for the host controller and the peripheral controller I Integrated multi-configuration FIFO I Double-buffering scheme increases throughput and facilitates real-time data transfer I Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low ...
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... NXP Semiconductors N Bus-powered or self-powered capability with suspend mode N Slave DMA, fully autonomous and supports multiple configurations N Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT endpoint N Integrated 8 kB memory N Software-controllable connection to the USB bus, SoftConnect SAF1761_1 Product data sheet Rev. 01 — ...
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... NXP Semiconductors 3. Applications The SAF1761 can be used to implement a dual-role USB device in any application, USB host or USB peripheral, depending on the cable connection. If the dual-role device is connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role device can also be connected any other USB host and behave like a typical USB peripheral ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name Description SAF1761BE LQFP128 plastic low profile quad flat package; 128 leads; body 14 SAF1761_1 Product data sheet Rev. 01 — 18 November 2009 SAF1761 Hi-Speed USB OTG controller Version 20 1.4 mm SOT425-1 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 5. Block diagram 47, 49, 51, 52 78, 80 DATA[15:0]/DATA[31:0] 82, 84, 86, 87 98, 100 to 103, 105 17 A[17:1] CS_N 106 RD_N 107 WR_N 108 DC_IRQ 111 HC_IRQ 112 DC_DREQ 113 HC_DREQ 114 HC_DACK 116 DC_DACK 117 124 C_B ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin Type LQFP128 OC3_N 1 AI/I REF5V GNDA 4 G REG1V8 CC(5V0 CC(5V0) GND(OSC REG3V3 CC(I/O) XTAL1 11 AI XTAL2 12 AO SAF1761_1 Product data sheet 1 SAF1761BE 38 Pin configuration (LQFP128); top view ...
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... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type LQFP128 CLKIN 13 I GNDD 14 G GND(RREF1 RREF1 16 AI GNDA 17 G DM1 18 AI/O GNDA 19 G DP1 20 AI/O PSW1_N 21 OD GND(RREF2 RREF2 23 AI GNDA 24 G DM2 25 AI/O GNDA 26 G DP2 27 AI/O PSW2_N 28 OD ...
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... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type LQFP128 DATA4 42 I/O DATA5 43 I/O GNDD 44 G DATA6 45 I/O DATA7 46 I/O DATA8 47 I CC(I/O) DATA9 49 I/O REG1V8 50 P DATA10 51 I/O DATA11 52 I/O GNDC 53 G DATA12 54 I/O GNDD 55 G DATA13 56 I/O DATA14 ...
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... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type LQFP128 DATA19 64 I/O DATA20 65 I/O DATA21 66 I CC(I/O) DATA22 68 I/O DATA23 69 I/O DATA24 70 I/O GNDD 71 G DATA25 72 I/O DATA26 73 I/O DATA27 74 I CC(I/O) DATA28 76 I/O DATA29 77 I/O DATA30 78 I/O GNDD 79 G DATA31 ...
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... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type LQFP128 GNDC GNDD CC(I/ A10 96 I A11 97 I A12 98 I GNDD 99 G A13 100 I A14 101 I A15 102 I A16 103 I V 104 P CC(I/O) A17 105 I CS_N 106 I RD_N 107 I SAF1761_1 Product data sheet ...
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... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type LQFP128 WR_N 108 I GNDD 109 G BAT_ON_N 110 OD DC_IRQ 111 O HC_IRQ 112 O DC_DREQ 113 O HC_DREQ 114 O V 115 P CC(I/O) HC_DACK 116 I DC_DACK 117 I REG1V8 118 P HC_SUSPEND 119 I/OD /WAKEUP_N DC_SUSPEND 120 I/OD ...
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... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type LQFP128 C_B 124 AI/O C_A 125 AI/O V 126 P CC(C_IN) OC1_N/V 127 (AI/O)(I) This pin tolerant and has multiple functions: BUS OC2_N 128 AI/I [1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. ...
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... NXP Semiconductors 7. Functional description 7.1 SAF1761 internal architecture: advanced NXP slave host controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the advanced NXP slave host controller. The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the SAF1761 is adapted from Universal Serial Bus Rev ...
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... NXP Semiconductors Fig 3. 7.1.1 Internal clock scheme and port selection The SAF1761 has three ports. Fig 4. SAF1761_1 Product data sheet EHCI ROOT HUB PORTSC1 ENUMERATION AND POLLING USING ACTUAL PTDs INTERNAL HUB (TT) PORT2 PORT1 Internal hub Figure 4 PORT 2 PORT 1 XOSC PORT 3 ...
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... NXP Semiconductors Port 2 does not need to be enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by external pull-up resistors, if not used. The DP and DM of the unused ports need not be externally pulled HIGH because there are internal pull-down resistors on each port that are enabled by default. ...
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... NXP Semiconductors The total amount of memory allocated to the payload determines the maximum transfer size specifi PTD, a larger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context switching, resulting in better CPU usage. A larger buffer also implies a larger amount of data can be transferred. The transfer, however, can be done over a longer period of time, to maintain the overall system performance ...
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... NXP Semiconductors The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously fill up another block area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping or delaying any other USB transaction or corrupting the RAM data. ...
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... NXP Semiconductors Table 4. Memory map ISO INT ATL Payload Both the CPU interface logic and the USB host controller require access to the internal SAF1761 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s ...
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... NXP Semiconductors • The address written to the Memory register is incremented and used to successively pre-fetch data from the memory irrespective of the value on the address bus for each bank, until a new value for a bank is written to the Memory register. This is valid only when the address refers to the memory space (400h to FFFFh). ...
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... NXP Semiconductors of that burst. It will be reasserted shortly after the DACK de-assertion, as long as the DMA transfer counter was not reached. DREQ will be de-asserted on the last cycle when the DMA transfer counter is reached and will not be reasserted until the DMA reprogramming is performed. Both DREQ and DACK signals are programmable as active LOW or active HIGH, according to the system requirements ...
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... NXP Semiconductors size. The transfer size can be an odd or even number of bytes, as required. If the transfer size is an odd number of bytes, the number of bytes transferred by the systems DMA is equal to the next multiple of two for the 16-bit data bus width or four for the 32-bit data bus width. For a write operation, however, only the specified odd number of bytes in the SAF1761 memory will be affected. – ...
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... NXP Semiconductors The asserted bits in the HcInterrupt register can be cleared by writing back the same value to the HcInterrupt register. This means that writing logic 1 to each of the set bits will reset the corresponding bits to the initial inactive state. The IRQ generation rules that apply according to the preceding settings are: • ...
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... NXP Semiconductors The OR function: If any of the PTDs are done, an IRQ for each of the PTD will be raised. Table 5. PTD 7.5 Phase-Locked Loop (PLL) clock multiplier The internal PLL requires a 12 MHz input, which can MHz crystal MHz clock already existing in the system with a precision better than 50 use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI) ...
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... NXP Semiconductors HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N require pull-up resistors because in the SAF1761 suspended state these pins become 3-state and can be pulled down, driving them externally by switching the processors GPIO lines to output mode to generate the SAF1761 wake-up. The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are 3-state output and also input to the internal wake-up logic ...
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... NXP Semiconductors cost. This circuit offers an easy solution at no extra hardware cost on the board. The port power will automatically be disabled by the SAF1761 on an overcurrent event occurrence, by de-asserting the PSWn_N signal without any software intervention. When using the integrated analog overcurrent detection, the range of the overcurrent detection voltage for the SAF1761 120 mV ...
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... NXP Semiconductors 7.8 Power supply Figure 7 (1) Each supply voltage pin must be connected to a 100 nF decoupling capacitor ( electrolytic or tantalum capacitor is required on any one of the pins 118. Fig 7. SAF1761_1 Product data sheet shows the SAF1761 power supply connection. V CC(5V0 10, 40, 48, ...
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... NXP Semiconductors Figure 8 (1) Each supply voltage pin must be connected to a 100 nF decoupling capacitor ( electrolytic or tantalum capacitor is required on any one of the pins 118. Fig 8. 7.8.1 Hybrid mode Table 6 Table 6. Voltage V CC(5V0) V CC(I/O) In hybrid mode (see transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the ...
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... NXP Semiconductors (1) Each supply voltage pin must be connected to a 100 nF decoupling capacitor ( electrolytic or tantalum capacitor is required on any one of the pins 118. Fig 9. Table 7 Table 7. Pins DATA[31:0], A[17:1], TEST, HC_IRQ, DC_IRQ, HC_DREQ, DC_DREQ, HC_DACK, DC_DACK, HC_SUSPEND/WAKEUP_N, DC_SUSPEND/WAKEUP_N CS_N, RESET_N, RD_N, WR_N ...
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... NXP Semiconductors 7.9 Power-On Reset (POR) Figure 10 starts with a HIGH at t0. At t1, the detector will see the passing of the trip level V and a delay element will add another too short, less than 11 ms, the PORP will not react and will remain LOW. A HIGH on PORP will be generated whenever REG1V8 drops below V (1) PORP = Power-On Reset Pulse ...
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... NXP Semiconductors 8. Host controller Table 8 • All registers range from 0000h to 03FFh. These registers can be read or written as double word, which is 32-bit data. In case of a 16-bit data bus width, two subsequent accesses are necessary to complete the register read or write cycle. • Operational registers range from 0000h to 01FFh. Host controller-specific and OTG controller-specifi ...
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... NXP Semiconductors Table 8. Address 0338h 033Ch 0340h 0344h 0354h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register The bit description of the Capability Length (CAPLENGTH) register is given in Table 9. Bit 8.1.2 HCIVERSION register Table 10 (HCIVERSION) register ...
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... NXP Semiconductors 8.1.3 HCSPARAMS register The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that are structural parameters. The bit allocation is given in Table 11. HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit allocation Bit 31 Symbol Reset 0 Access R Bit 23 Symbol Reset ...
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... NXP Semiconductors 8.1.4 HCCPARAMS register The Host Controller Capability Parameters (HCCPARAMS) register is a four byte register, and the bit allocation is given in Table 13. HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit allocation Bit 31 Symbol Reset 0 Access R Bit 23 Symbol Reset 0 Access R Bit ...
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... NXP Semiconductors 8.2 EHCI operational registers 8.2.1 USBCMD register The USB Command (USBCMD) register indicates the command to be executed by the serial host controller. Writing to this register causes a command to be executed. shows the USBCMD register bit allocation. Table 15. USBCMD - USB Command register (address 0020h) bit allocation ...
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... NXP Semiconductors 8.2.2 USBSTS register The USB Status (USBSTS) register indicates pending interrupts and various states of the host controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software clears register bits by writing ones to them. The bit allocation is given in Table 17 ...
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... NXP Semiconductors 8.2.3 USBINTR register The USB Interrupt (USBINTR) register is a read or write register located at 0028h. All the bits in this register are reserved. 8.2.4 FRINDEX register The Frame Index (FRINDEX) register is used by the host controller to index into the periodic frame list. The register updates every 125 s (once each microframe). Bits are used to select a particular entry in the periodic frame list during periodic schedule execution ...
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... NXP Semiconductors 8.2.5 CONFIGFLAG register The bit allocation of the Configure Flag (CONFIGFLAG) register is given in Table 21. CONFIGFLAG - Configure Flag register (address 0060h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access ...
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... NXP Semiconductors Table 23. PORTSC1 - Port Status and Control 1 register (address 0064h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol PIC[1:0] Reset 0 Access R Bit 7 Symbol SUSP FPR Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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... NXP Semiconductors Table 24. PORTSC1 - Port Status and Control 1 register (address 0064h) bit description Bit Symbol Description 2 PED Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. 1 ECSC Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change. 0 ECCS Current Connect Status: Logic 1 indicates a device is present on the port. Logic 0 indicates no device is present ...
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... NXP Semiconductors respective memory space, would be checked, especially if only a few PTDs are defined. The LastPTD bit must be normally set to a higher position than any other position indicated by the NextPTDPointer from an active PTD. 8.2.10 INT PTD Done Map register The bit description of the register is given in Table 28 ...
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... NXP Semiconductors 8.2.13 ATL PTD Done Map register Table 31 Table 31. ATL PTD Done Map register (address 0150h) bit description Bit Symbol Access ATL_PTD_DONE_ R MAP[31:0] This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will refl ...
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... NXP Semiconductors 8.3 Configuration registers 8.3.1 HW Mode Control register Table 34 Table 34. HW Mode Control - Hardware Mode Control register (address 0300h) bit allocation Bit 31 Symbol ALL_ATX_ RESET Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol ANA_DIGI_ OC Reset ...
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... NXP Semiconductors Table 35. HW Mode Control - Hardware Mode Control register (address 0300h) bit description Bit Symbol 8 DATA_BUS_WIDTH DACK_POL 5 DREQ_POL INTR_POL 1 INTR_LEVEL 0 GLOBAL_INTR_EN 8.3.2 HcChipID register Read this register to get the ID of the SAF1761. The upper word of the register contains the hardware version number and the lower word contains the chip ID. ...
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... NXP Semiconductors 8.3.3 HcScratch register This register is for testing and debugging purposes only. The value read back must be the same as the value that was written. The bit description of this register is given in Table 37. HcScratch - Host Controller Scratch register (address 0308h) bit description ...
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... NXP Semiconductors 8.3.5 HcDMAConfiguration register The bit allocation of the HcDMAConfiguration register is given in Table 40. HcDMAConfiguration - Host Controller Direct Memory Access Configuration register (address 0330h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W ...
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... NXP Semiconductors 8.3.6 HcBufferStatus register The HcBufferStatus register is used to indicate the HC that a particular PTD buffer (that is, ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets the Buffer Filled bit of a particular transfer in the HcBufferStatus register, the HC will start traversing through PTD headers that are not marked for skipping and are valid PTDs ...
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... NXP Semiconductors 8.3.7 ATL Done Timeout register The bit description of the ATL Done Timeout register is given in Table 44. ATL Done Timeout register (address 0338h) bit description Bit Symbol Access ATL_DONE_TIME R/W OUT[31:0] 8.3.8 Memory register The Memory register contains the base memory read address and the respective bank. ...
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... NXP Semiconductors 8.3.9 Edge Interrupt Count register Table 47 Table 47. Edge Interrupt Count register (address 0340h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value ...
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... NXP Semiconductors 8.3.10 DMA Start Address register This register defines the start address select for the DMA read and write operations. See Table 49 Table 49. DMA Start Address register (address 0344h) bit allocation Bit 31 Symbol Reset 0 Access W Bit 23 Symbol Reset 0 Access W Bit ...
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... NXP Semiconductors 8.3.11 Power-Down Control register This register is used to turn off power to the internal blocks of the SAF1761 to obtain maximum power savings. Table 51. Power-Down Control register (address 0354h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 1 Access R/W R/W ...
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... NXP Semiconductors Table 52. Power-Down Control register (address 0354h) bit description [1] Bit Symbol 11 PORT2_PD 10 VBATDET_PWR BIASEN 4 VREG_ON 3 OC3_PWR 2 OC2_PWR 1 OC1_PWR 0 HC_CLK_EN [1] For a 32-bit operation, the default wake-up counter value For a 16-bit operation, the wake-up counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization. ...
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... NXP Semiconductors 8.4 Interrupt registers 8.4.1 HcInterrupt register The bits of this register indicate the interrupt source, defining the events that determined the INT generation. Clearing the bits that were set because of the events listed is done by writing back logic 1 to the respective position. All bits must be reset before enabling new interrupt events ...
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... NXP Semiconductors Table 54. HcInterrupt - Host Controller Interrupt register (address 0310h) bit description Bit Symbol Description reserved; write reset value 10 OTG_IRQ OTG_IRQ: Indicates that an OTG event occurred. The IRQ line will be asserted if the respective enable bit in the HcInterruptEnable register is set. 0 — No OTG event 1 — ...
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... NXP Semiconductors 8.4.2 HcInterruptEnable register This register allows enabling or disabling of the IRQ generation because of various events as described in Table 55. HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit ...
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... NXP Semiconductors Table 56. HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit description Bit Symbol Description 7 INT_IRQ_E INT IRQ Enable: Controls the IRQ assertion when one or more INT PTDs matching the INT IRQ Mask AND or INT IRQ Mask OR register bits combination are completed. ...
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... NXP Semiconductors 8.4.5 ATL IRQ Mask OR register Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a hardware IRQ mask for each PTD done map. See see Section Table 59. ATL IRQ Mask OR register (address 0320h) bit description Bit Symbol ...
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... NXP Semiconductors 8.5 Proprietary Transfer Descriptor (PTD) The standard EHCI data structures as described in Interface Specification for Universal Serial Bus Rev. 1.0” operation that is managed by the hardware state machine. The PTD structures of the SAF1761 are translations of the EHCI data structures that are optimized for the SAF1761 ...
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... NXP Semiconductors 2. If the current PTD is active and not done, perform the transaction. 3. Follow the NextPTD pointer as specified in bits DW4 combined with LastPTD, the LastPTD setting must higher address than the NextPTD specified. Both have to be set in a logical manner. ...
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Table 63. High-speed bulk IN and OUT: bit allocation Bit DW7 DW5 [1] DW3 Cerr ...
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... NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access DW7 reserved - DW6 reserved - DW5 reserved - DW4 reserved - — writes - NextPTDPointer SW — writes - [4:0] DW3 — sets HW — resets — writes - — writes - — writes - SW — writes - 59 reserved - — writes HW — ...
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... NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access Cerr[1:0] HW — writes SW — writes NakCnt[3:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred SW — writes [14:0] DW2 reserved - RL[3:0] SW — writes - 24 reserved - DataStart SW — writes - Address[15: reserved ...
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... NXP Semiconductors Table 64. High-speed bulk IN and OUT: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes - Mult[1:0] SW — writes - MaxPacket SW — writes - Length[10: NrBytesTo SW — writes - Transfer[14: reserved - — sets HW — resets 8.5.2 High-speed isochronous IN and OUT Table 65 Transfer Descriptor (iTD). ...
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Table 65. High-speed isochronous IN and OUT: bit allocation Bit ...
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... NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW7 ISOIN_7[11:0] HW — writes ISOIN_6[11:0] HW — writes ISOIN_5[11:4] HW — writes DW6 ISOIN_5[3:0] HW — writes ISOIN_4[11:0] HW — writes ISOIN_3[11:0] HW — writes ISOIN_2[11:8] HW — writes DW5 ISOIN_2[7:0] HW — writes ISOIN_1[11:0] HW — writes ISOIN_0[11:0] HW — ...
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... NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW3 — sets — writes — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address[15: Frame[7:0] SW — writes DW1 reserved - — writes EPType[1:0] SW — writes ...
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... NXP Semiconductors Table 66. High-speed isochronous IN and OUT: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — resets SW — sets 8.5.3 High-speed interrupt IN and OUT Table 67 Descriptor (pTD). SAF1761_1 ...
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Table 67. High-speed interrupt IN and OUT: bit allocation Bit ...
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... NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW7 INT_IN_7[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[11:4] HW — writes DW6 INT_IN_5[3:0] HW — writes INT_IN_4[11:0] HW — writes INT_IN_3[11:0] HW — writes INT_IN_2[11:8] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[11:0] HW — writes INT_IN_0[11:0] HW — ...
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... NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW3 — writes SW — writes — writes reserved - — writes SW — writes Cerr[1:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address[15:0] ...
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... NXP Semiconductors Table 68. High-speed interrupt IN and OUT: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets Table 69. Microframe description b Rate 1 1 SOF 2 2 SOF 3 4 SOF ...
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Table 70. Start and complete split for bulk: bit allocation Bit ...
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... NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol DW7 reserved DW6 reserved DW5 reserved DW4 reserved NextPTDPointer[4:0] SW — writes DW3 reserved Cerr[1: NakCnt[3: reserved NrBytes Transferred[14:0] DW2 SAF1761_1 Product data sheet Access Value Description - - - - - ...
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... NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol reserved RL[3:0] 24 reserved DataStartAddress [15: reserved DW1 HubAddress[6: PortNumber[6: SE[1:0] 47 reserved EPType[1: Token[1: DeviceAddress[6: EndPt[3:1] SAF1761_1 Product data sheet …continued Access Value Description - - - SW — writes - Reload set to 0h, hardware ignores the NakCnt value. ...
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... NXP Semiconductors Table 71. Start and complete split for bulk: bit description Bit Symbol DW0 31 EndPt[ reserved MaximumPacket Length[10: NrBytesTo Transfer[14: reserved 0 V Table 72. SE description Bulk Control I/O I/O I/O I/O 8.5.5 Start and complete split for isochronous Table 73 isochronous Transfer Descriptor (siTD). ...
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Table 73. Start and complete split for isochronous: bit allocation Bit ...
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... NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access DW7 reserved - ISO_IN_7[7:0] HW — writes DW6 ISO_IN_6[7:0] HW — writes ISO_IN_5[7:0] HW — writes ISO_IN_4[7:0] HW — writes ISO_IN_3[7:0] HW — writes DW5 ISO_IN_2[7:0] HW — writes ISO_IN_1[7:0] HW — writes ISO_IN_0[7:0] HW — writes ...
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... NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates 58 reserved - — writes SW — writes reserved - NrBytes HW — writes Transferred [11:0] ...
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... NXP Semiconductors Table 74. Start and complete split for isochronous: bit description Bit Symbol Access DW0 31 EndPt[0] SW — writes reserved - TT_MPS_Len SW — writes [10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets 8.5.6 Start and complete split for interrupt Table 75 SAF1761_1 Product data sheet ...
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Table 75. Start and complete split for interrupt: bit allocation Bit ...
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... NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] HW — writes INT_IN_4[7:0] HW — writes INT_IN_3[7:0] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[7:0] HW — writes INT_IN_0[7:0] HW — writes ...
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... NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates 58 reserved - — writes SW — writes Cerr[1:0] HW — writes SW — writes reserved ...
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... NXP Semiconductors Table 76. Start and complete split for interrupt: bit description Bit Symbol Access Token[1:0] SW — writes DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — writes reserved - MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets Table 77 ...
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... NXP Semiconductors 9. OTG controller 9.1 Introduction OTG is a supplement to the Hi-Speed USB specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals primarily targeted at portable devices because it addresses concerns related to such devices, such as a small connector and low power. Non-portable devices, even standard hosts, can also benefi ...
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... NXP Semiconductors peripheral, and the A-device assumes the role of a host. The A-device detects that the B-device can support HNP by getting the OTG descriptor from the B-device. The A-device will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into the suspend state ...
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... NXP Semiconductors 9.4 Host Negotiation Protocol (HNP) HNP is used to transfer control of the host role between the default host (A-device) and the default peripheral (B-device) during a session. When the A-device is ready to give up its role as a host, it will condition the B-device using SetFeature (b_hnp_enable) and will go into suspend ...
Page 87
... NXP Semiconductors 6. The A-device detects lack of bus activity for more than 3 ms and turns off its DP pull-up. Alternatively, if the A-device has no further need to communicate with the B-device, the A-device may turn off V 7. The B-device turns on its pull-up. 8. After waiting ensure that the DP line is not HIGH because of the residual ...
Page 88
... NXP Semiconductors START id | a_bus_req | (a_sess_vld/ & b_conn/) a_wait_vfall drv_vbus/ loc_conn/ loc_sof a_bus_drop a_peripheral drv_vbus loc_conn loc_sof/ b_conn/ & a_set_b_hnp_en id | a_bus_drop | a_aidl_bdis_tmout a_suspend drv_vbus loc_conn/ loc_sof/ Fig 14. Dual-role A-device state diagram SAF1761_1 Product data sheet a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof a_bus_drop | a_wait_bcon_tmout ...
Page 89
... NXP Semiconductors START id/ | b_sess_vld/ b_host chrg_vbus/ loc_conn/ loc_sof a_conn b_wait_acon chrg_vbus/ loc_conn/ loc_sof/ Fig 15. Dual-role B-device state diagram 9.4.3 HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality implemented in the microprocessor system that is connected to the SAF1761. The SAF1761 provides ...
Page 90
... NXP Semiconductors The following steps are required to enable an OTG interrupt: 1. Set the polarity and level-triggering or edge-triggering mode of the HW Mode Control register. 2. Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt Enable Fall registers. 3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10). ...
Page 91
... NXP Semiconductors Table 80. Address OTG Interrupt registers 0378h 037Ch 0380h 0384h OTG Timer register 0388h 038Ch Table 81. Address Device ID registers 0370h 0372h OTG Control register 0374h 0376h OTG Interrupt registers 0378h 037Ah 037Ch 037Eh 0380h 0382h 0384h 0386h OTG Timer register ...
Page 92
... BDIS_ACON_ Enables the A-device to connect if the B-device disconnect is detected EN SAF1761_1 Product data sheet shows the bit description of the register. Access Value Description R 04CCh NXP Semiconductors Vendor ID Access Value Description R 1761h Product ID of the SAF1761 shows the bit allocation of the register [1] reserved ...
Page 93
... NXP Semiconductors Table 85. OTG Control register (address set: 0374h, clear: 0376h) bit description [1] Bit Symbol Description 7 SW_SEL_HC In software HNP mode, this bit selects between the host controller and the peripheral controller — Host controller connected to ATX DC 1 — Peripheral controller connected to ATX This bit is set to logic 1 by hardware when there is an event corresponding to the BDIS_ACON interrupt ...
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... NXP Semiconductors 9.5.3 OTG Interrupt registers 9.5.3.1 OTG Status register This register indicates the current state of the signals that can generate an interrupt. The bit allocation of the register is given in Table 86. OTG Status register (address 0378h) bit allocation Bit 15 Symbol Reset 0 Access R Bit ...
Page 95
... NXP Semiconductors Bit 7 Symbol B_SESS_ BDIS_ END ACON Reset 0 Access R/S/C R/S/C [1] The reserved bits should always be written with the reset value. Table 89. OTG Interrupt Latch register (address set: 037Ch, clear: 037Eh) bit description Bit Symbol OTG_TMR_TIMEOUT OTG timer time-out 8 B_SE0_SRP ...
Page 96
... NXP Semiconductors Table 91. OTG Interrupt Enable Fall register (address set: 0380h, clear: 0382h) bit description Bit Symbol Description 4 RMT_CONN IRQ asserted on RMT_CONN removal 3 ID IRQ asserted on the ID pin transition from HIGH to LOW 2 - reserved 1 A_B_SESS_VLD IRQ asserted on removing A-session valid for the A-device or B-session valid for the ...
Page 97
... NXP Semiconductors 9.5.4 OTG Timer register 9.5.4.1 OTG Timer register This is a 32-bit register organized as two 16-bit fields. These two fields have separate set and clear addresses. Table 94. OTG Timer register (address low word set: 0388h, low word clear: 038Ah; high word set: 038Ch, high ...
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... NXP Semiconductors 10. Peripheral controller 10.1 Introduction The USB protocol and data transfer operations of the peripheral controller are executed using external firmware. The external microcontroller or microprocessor can access the peripheral controller-specific registers through the local bus interface. The transfer of data between a microprocessor and the peripheral controller can be done in PIO mode or programmed DMA mode ...
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... NXP Semiconductors 0280h). The default value is 1Eh, which indicates that the interrupt pulse width The minimum interrupt pulse width is approximately 30 ns when set to logic 1. Do not write a zero to this register. The interrupt polarity must also be correctly set. Remark: DMA can apply to all endpoints on the chip. It, however, can only take place for one endpoint at a time ...
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... NXP Semiconductors Setting bit GDMA Stop in the DMA Command register (address: 0230h) will force the DMA to stop and bit GDMA_STOP in the DMA Interrupt Reason register (address: 0250h) will be set to indicate this event. Setting bit Reset DMA in the DMA Command register (address: 0230h) will force the DMA to stop and initialize the DMA core to its power-on reset state ...
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... NXP Semiconductors 10.3 Peripheral controller-specific registers Table 97. Address Register Initialization registers 0200h 020Ch 0210h 0212h 0214h 0300h 0374h Data flow registers 022Ch 0228h 0220h 021Ch 021Eh 0204h 0208h DMA registers 0230h 0234h 0238h 023Ch 0250h 0254h 0258h 0264h General registers ...
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... NXP Semiconductors In response to standard USB request SET_ADDRESS, firmware must write the (enabled) peripheral address to the Address register, followed by sending an empty packet to the host. The new peripheral address is activated when the peripheral receives acknowledgment from the host for the empty packet token. ...
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... NXP Semiconductors Table 101. Mode register (address 020Ch) bit description Bit Symbol Description reserved 9 DMACLKON DMA Clock On: 1 — Supply clock to the DMA circuit. 0 — Power saving mode. The DMA circuit will stop completely to save power. 8 VBUSSTAT V BUS When implementing a pure host or peripheral, the OTG_DISABLE bit in the OTG Control register (374h) must be set to logic 1 so that the VBUSSTAT bit is updated with the correct value ...
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... NXP Semiconductors Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to logic 1, an interrupt will generate a pulse (edge-triggering). Table 102. Interrupt Configuration register (address 0210h) bit allocation ...
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... NXP Semiconductors Table 106. Debug register (address 0212h) bit allocation Bit Symbol Description reserved 0 DEBUG Always set this bit to logic 0 in both 16-bit and 32-bit accesses. 10.3.5 DcInterruptEnable register This register enables or disables individual interrupt sources. The interrupt for each endpoint can individually be controlled through the associated IEPnRX or IEPnTX bits, here n represents the endpoint number ...
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... NXP Semiconductors Table 108. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) Bit SAF1761_1 Product data sheet bit description Symbol Description - reserved EP7TX logic 1 enables interrupt from the indicated endpoint EP7RX logic 1 enables interrupt from the indicated endpoint EP6TX logic 1 enables interrupt from the indicated endpoint ...
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... NXP Semiconductors 10.4 Data flow registers 10.4.1 Endpoint Index register The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 byte, and the bit allocation is shown in Table 109. The following registers are indexed: • Buffer Length • ...
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... NXP Semiconductors Table 111. Addressing of endpoint buffers Buffer name SETUP Control OUT Control IN Data OUT Data IN 10.4.2 Control Function register The Control Function register performs the buffer management on endpoints. It consists of 1 byte, and the bit configuration is given in validate any enabled data endpoint. Before accessing this register, the Endpoint Index register must fi ...
Page 109
... NXP Semiconductors Table 113. Control Function register (address 0228h) bit description Bit Symbol Description 1 STATUS Status Acknowledge: Only applicable for control IN and OUT. This bit controls the generation of ACK or NAK during the status stage of a SETUP transfer automatically cleared when the status stage is completed and a SETUP token is received. No interrupt signal will be generated. 0 — ...
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... NXP Semiconductors Table 115. Data Port register (address 0220h) bit description Bit Symbol Access DATAPORT R/W [15:0] 10.4.4 Buffer Length register This register determines the current packet size (DATACOUNT) of the indexed endpoint FIFO. The bit description is given in The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint MaxPacketSize register is written (see required ...
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... NXP Semiconductors Remark: For the endpoint IN data transfer, firmware must ensure a 200 ns delay between writing of the data packet and reading the DcBufferStatus register. For the endpoint OUT data transfer, firmware must also ensure a 200 ns delay between the reception of the endpoint interrupt and reading the DcBufferStatus register. ...
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... NXP Semiconductors Table 120. Endpoint MaxPacketSize register (address 0204h) bit description Bit Symbol Description reserved NTRANS[1:0] Number of Transactions: High-Speed (HS) mode only. 00 — One packet per microframe 01 — Two packets per microframe 10 — Three packets per microframe 11 — reserved These bits are applicable only for isochronous or interrupt transactions. ...
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... NXP Semiconductors Table 122. Endpoint Type register (address 0208h) bit description Bit Symbol Description reserved 4 NOEMPKT No Empty Packet: Logic 0 causes the SAF1761 to return a null length packet for the IN token after the DMA IN transfer is complete. Set to logic 1 to disable the generation of the null length packet ...
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... NXP Semiconductors Table 123. Control bits for GDMA read or write (opcode = 00h/01h) Control bits Description Mode register DMACLKON Set DMACLKON to logic 1 DcDMAConfiguration register MODE[1:0] Determines the active read or write data strobe signals WIDTH Selects the DMA bus width: 16-bit or 32-bit ...
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... NXP Semiconductors Table 126. DMA commands …continued Code Name Description 0Fh Clear Buffer Clear Buffer: Request from the microcontroller to clear the endpoint buffer, after a DMA-to-USB data transfer. Logic 1 clears the TX buffer of the indexed endpoint; the RX buffer is not affected. The TX buffer is automatically cleared once data is sent on the USB bus ...
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... NXP Semiconductors Bit 7 Symbol Reset 0 Bus reset 0 Access R/W Table 128. DMA Transfer Counter register (address 0234h) bit description Bit Symbol DMACR4, DMACR[31:24 DMACR3, DMACR[23:16 DMACR2, DMACR[15: DMACR1, DMACR[7:0] 10.5.4 DcDMAConfiguration register This register defines the DMA configuration for GDMA mode. The DcDMAConfiguration register consists of 2 bytes. The bit allocation is given in Table 129. DcDMAConfi ...
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... NXP Semiconductors Table 130. DcDMAConfiguration - Device Controller Direct Memory Access Configuration register (address 0238h) bit description …continued Bit Symbol MODE[1: WIDTH 10.5.5 DMA Hardware register The DMA Hardware register consists of 1 byte. The bit allocation is shown in This register determines the polarity of bus control signals (DACK and DREQ). ...
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... NXP Semiconductors 10.5.6 DMA Interrupt Reason register This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a DMA command is executed. An interrupt source is cleared by writing logic 1 to the corresponding bit. On detecting the interrupt, the external microprocessor must read the DMA Interrupt Reason register and mask it with the corresponding bits in the DMA Interrupt Enable register to determine the source of the interrupt ...
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... NXP Semiconductors 10.5.7 DMA Interrupt Enable register This 2 bytes register controls the interrupt generation of the source bits in the DMA Interrupt Reason register. The bit allocation is given in given in Logic 1 enables the interrupt generation. The values after a (bus) reset are logic 0 (disabled). Table 136. DMA Interrupt Enable register (address 0254h) bit allocation ...
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... NXP Semiconductors 10.5.9 DMA Burst Counter register The bit allocation of the register is given in Table 139. DMA Burst Counter register (address 0264h) bit allocation Bit 15 Symbol reserved Reset 0 Bus reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Bus reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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... NXP Semiconductors Table 141. DcInterrupt - Device Controller Interrupt register (address 0218h) bit allocation Bit 31 Symbol Reset 0 Bus reset 0 Access R/W R/W Bit 23 Symbol EP6TX EP6RX Reset 0 Bus reset 0 Access R/W R/W Bit 15 Symbol EP2TX EP2RX Reset 0 Bus reset 0 Access R/W R/W ...
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... NXP Semiconductors Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit description Bit Symbol Description 9 - reserved 8 EP0SETUP logic 1 indicates that a SETUP token was received on endpoint 0 7 VBUS Logic 1 indicates a transition from LOW to HIGH on V When implementing a pure host or peripheral, the OTG_DISABLE bit in the OTG Control register (374h) must be set to logic 1 so that the VBUS bit is updated with the correct value ...
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... NXP Semiconductors Table 145. Frame Number register (address 0274h) bit description Bit Symbol Description reserved MICROSOF[2:0] microframe number SOFR[10:0] frame number 10.6.4 DcScratch register This 16-bit register can be used by the firmware to save and restore information. For example, the device status before it enters the suspend state; see Table 146 ...
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... NXP Semiconductors Table 149. Unlock Device register (address 027Ch) bit description Bit Symbol Description ULCODE[15:0] Unlock Code: Writing data AA37h unlocks internal registers and FIFOs for writing, following a resume. 10.6.6 Interrupt Pulse Width register Table 150 Table 150. Interrupt Pulse Width register (address 0280h) bit description ...
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... NXP Semiconductors 11. Power consumption Table 153. Power consumption, typical values Number of ports working One port working (high-speed) V CC(5V0) V CC(5V0) V CC(5V0) V CC(5V0) Two ports working (high-speed) V CC(5V0) V CC(5V0) V CC(5V0) V CC(5V0) Three ports working (high-speed) V CC(5V0) V CC(5V0) V CC(5V0) V CC(5V0) The idle operating current, I initialized and without any devices connected ...
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... NXP Semiconductors 12. Limiting values Table 154. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V supply voltage (5.0 V) CC(5V0) V charge pump supply voltage CC(C_IN) V electrostatic discharge voltage ESD T storage temperature stg [1] Class 2 according to JEDEC JESD22-A114 . ...
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... NXP Semiconductors 14. Static characteristics Table 156. Static characteristics: digital pins [1] All digital pins , except pins ID, PSW1_N, PSW2_N, PSW3_N and BAT_ON_N +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage ...
Page 128
... NXP Semiconductors Table 160. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Input levels for high-speed V high-speed squelch detection HSSQ threshold voltage (differential signal amplitude) V high-speed disconnect detection ...
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... NXP Semiconductors Table 161. Static characteristics 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter V A-device V A_VBUS_VLD BUS V B-device session valid voltage B_SESS_VLD V B-device session valid hysteresis voltage hys(B_SESS_VLD) V B-device session end voltage B_SESS_END [1] Minimum trigger voltage at extreme low temperature ( 40 C). ...
Page 130
... NXP Semiconductors 15. Dynamic characteristics Table 163. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Crystal oscillator f clock frequency clk External clock input t external clock jitter J clock duty cycle V input voltage on pin XTAL1 i(XTAL1) t rise time ...
Page 131
... NXP Semiconductors Table 166. Dynamic characteristics: full-speed source electrical characteristics +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Driver characteristics t rise time FR t fall time FF t differential rise and fall time FRFM matching Data timing: see Figure 16 t source jitter for differential ...
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... NXP Semiconductors 15.1 Host timing 15.1.1 PIO timing 15.1.1.1 Register or memory write Fig 17. Register or memory write Table 168. Register or memory write +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t h11 t h21 t h31 t w11 t su11 t su21 t su31 3.6 V CC(I/O) ...
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... NXP Semiconductors 15.1.1.2 Register read Fig 18. Register read Table 169. Register read +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t su12 t su22 t w12 t d12 t d22 3.6 V CC(I/O) t su12 t su22 t w12 t d12 t d22 15.1.1.3 Register access CS_N WR_N RD_N Fig 19 ...
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... NXP Semiconductors Table 170. Register access +85 C; unless otherwise specified. amb Symbol t WHRL t RHRL t RHWL t WHWL [1] For EHCI operational registers, minimum value is 195 ns. 15.1.1.4 Memory read A[17:1] DATA CS_N WR_N RD_N Fig 20. Memory read Table 171. Memory read +85 C; unless otherwise specified. ...
Page 135
... NXP Semiconductors Table 171. Memory read +85 C; unless otherwise specified. amb Symbol t w13 t su13 t su23 15.1.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity of DREQ is active HIGH 15.1.2.1 Single cycle: DMA read Fig 21. DMA read (single cycle) Table 172 ...
Page 136
... NXP Semiconductors Table 172. DMA read (single cycle +85 C; unless otherwise specified. amb Symbol t a34 t a44 t h14 15.1.2.2 Single cycle: DMA write Fig 22. DMA write (single cycle) Table 173. DMA write (single cycle +85 C; unless otherwise specified. amb Symbol ...
Page 137
... NXP Semiconductors 15.1.2.3 Multi-cycle: DMA read Fig 23. DMA read (multi-cycle burst) Table 174. DMA read (multi-cycle burst +85 C; unless otherwise specified. amb Symbol 1.95 V CC(I/O) t a16 t a26 t d16 t w16 T cy16 t a36 t a46 t h16 3.6 V CC(I/O) t a16 t a26 t d16 ...
Page 138
... NXP Semiconductors 15.1.2.4 Multi-cycle: DMA write Fig 24. DMA write (multi-cycle burst) Table 175. DMA write (multi-cycle burst +85 C; unless otherwise specified. amb Symbol Parameter 1.95 V CC(I/O) T cy17 t su17 t h17 t a17 t a27 t a37 t h27 t a47 t w17 t a57 3.6 V CC(I/O) ...
Page 139
... NXP Semiconductors 15.2 Peripheral timing 15.2.1 PIO timing 15.2.1.1 PIO register read or write CS_N AD[17:1] (read) DATA[31:0] RD_N (write) DATA[31:0] WR_N Fig 25. SAF1761 register access timing: separate address and data buses (8051 style) Table 176. PIO register read or write +85 C; unless otherwise specified. ...
Page 140
... NXP Semiconductors Table 176. PIO register read or write +85 C; unless otherwise specified. amb Symbol Parameter t d68 3.6 V CC(I/O) Reading t w18 t su18 t h18 t d18 t d28 t d38 t d48 Writing t w28 t su28 t h28 t su38 t h38 t d58 t d68 15.2.1.2 PIO register access CS_N ...
Page 141
... NXP Semiconductors 15.2.2 DMA timing 15.2.2.1 DMA read or write (2) DREQ t su19 (1) DACK t su39 RD_N/WR_N (read) DATA [ (write) DATA [ DREQ is continuously asserted until the last transfer is done or the FIFO is full. Data strobes: RD_N (read) and WR_N (write). (1) Programmable polarity: shown as active LOW. ...
Page 142
... NXP Semiconductors Table 178. DMA read or write +85 C; unless otherwise specified. amb Symbol Parameter t h19 t w19 t w29 t d29 t h29 t h39 t su29 t su39 t a19 SAF1761_1 Product data sheet …continued DREQ hold time after last strobe on RD_N/WR_N pulse width RD_N/WR_N recovery time ...
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... NXP Semiconductors 16. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 146
... NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Appendix 18.1 Errata added on 2009-04-20 18.1.1 Problem description When the SAF1761 is programmed to perform infinite retries on Not Acknowledged (NAK) IN tokens, the SAF1761 does not generate the retry IN tokens on its own ...
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... NXP Semiconductors 18.1.3.2 Hardware retry mechanism Set program register RL = 0000b, NakCnt = 0000b and Cerr = 10b. In this case, interrupt will not be generated for NAKs and hardware will retry indefinitely, until the device responds with a data or an ACK. 18.2 Errata added on 2009-04-20 18 ...
Page 148
... NXP Semiconductors Fig 30. Peripheral Controller recognizing the number of bytes received During a short packet transfer, the counter will always be decremented by 4 bytes or 2 bytes, depending on the bus width setting although other operations are not affected. The problem occurs when sending the last byte. The Peripheral Controller DMA Transfer Counter register will still be decremented by 4 bytes or 2 bytes, depending on the settings of the bus width even though only 1 byte of data is sent ...
Page 149
... NXP Semiconductors • When an attached device, with the remote wake-up feature, initiates a resume on the USB bus • If the HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are pulled LOW to wake up from suspend. With any one of the preceding events, the SAF1761 USB controller wakes-up from suspend and the clock starts functioning, and all functionalities work normally. ...
Page 150
... NXP Semiconductors Fig 32. Waveform for DC_SUSPEND/WAKEUP_N pin goes LOW but the clock is not 18.4.2 Implication For low-power applications, the SAF1761 can be put into the suspend state on both the Host Controller and Peripheral Controller sides. But to enter deep-sleep suspend mode, the clock must be turned off so that the current consumption can be reduced to less than 400 A ...
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... NXP Semiconductors 18.5.2 Implication Moderate 18.5.3 Workaround After performing a write access to the Endpoint Index or Control Function register, the RD_N signal can only be asserted 60 ns after the WR_N signal is de-asserted (see Figure 33). CS_N WR_N RD_N A[17:1] Fig 33. Timing diagram for reading Endpoint Index register after performing a write 18 ...
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... NXP Semiconductors 18.6.2 Implication The implication will be serious if the device is getting disconnected during the data transfer. 18.6.3 Workaround The software workaround will check if a port has suddenly been disabled (Port Enable bit cleared) when a device is still connected to the port. Once it detects this condition, the software workaround will perform the necessary steps to re-enable the port and reschedule any halted transfer because of the error condition ...
Page 153
... NXP Semiconductors To determine and resolve the problematic condition, the following steps are taken: • Check the completion status once a PTD scheduled towards a full-speed or low-speed device and connected through the internal hub is completed. • If the PTD has been completed successfully, clear the variable that keeps track of the number of the times the port has been force enabled. • ...
Page 154
... NXP Semiconductors 18.7.3 Workaround The Peripheral Software driver needs to be modified to poll A_B_SESS_VLD bit in the OTG Status Register (0x0378) instead of VBUSSTAT of the Mode Register (020Ch) to detect the presence of the SAF1761 peripheral connection with USB Host. This bit has lower trigger voltage. ...
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... NXP Semiconductors 19. Abbreviations Table 181. Abbreviations Acronym ACK ASIC ATL ATX BCD CPU CS DC DMA EHCI EMI EOP EOT ESR FIFO FLS GDMA GPIO GPS HC HNP IEC INT IRQ ISO ISR iTD ITL I/O LS LSByte MSByte NAK NYET OC OHCI SAF1761_1 Product data sheet ...
Page 156
... NXP Semiconductors Table 181. Abbreviations Acronym OTG PC PCI PID PIO PLL PMOS POR PORP PPC pTD PTD RAM RISC R/S R/W SE0 SE1 SIE siTD SOF SRAM SRP USB XOSC [1] Letter X became a synonym for “crystal”. SAF1761_1 Product data sheet …continued ...
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... NXP Semiconductors 20. Glossary Bulk transfer — One of the four USB transfer types aperiodic, large burst communication, typically used for a transfer, which works with any available bandwidth. A bulk transfer can also be delayed until more bandwidth becomes available. Endpoint — A uniquely addressable portion of an USB device that is the source or sink of information in a communication fl ...
Page 158
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 25. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .5 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 3. Port connection scenarios . . . . . . . . . . . . . . . .16 Table 4. Memory address . . . . . . . . . . . . . . . . . . . . . . .19 Table 5. Using the IRQ Mask AND or IRQ Mask OR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 6. Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 7. Pin status during hybrid mode . . . . . . . . . . . . .29 Table 8. Host controller-specific register overview . . . .31 Table 9. ...
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... NXP Semiconductors Table 49. DMA Start Address register (address 0344h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 50. DMA Start Address register (address 0344h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 51. Power-Down Control register (address 0354h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 52. Power-Down Control register (address 0354h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 53. HcInterrupt - Host Controller Interrupt register (address 0310h) bit allocation ...
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... NXP Semiconductors bit description . . . . . . . . . . . . . . . . . . . . . . . .104 Table 104.Debug mode settings . . . . . . . . . . . . . . . . . . .104 Table 105.Debug register (address 0212h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .104 Table 106.Debug register (address 0212h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105 Table 107.DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105 Table 108.DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) bit description ...
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... NXP Semiconductors Table 155.Recommended operating conditions . . . . . . .126 Table 156.Static characteristics: digital pins . . . . . . . . . .127 Table 157.Static characteristics: pins PSW1_N, PSW2_N and PSW3_N . . . . . . . . . . . . . . . . .127 Table 158.Static characteristics: POR . . . . . . . . . . . . . .127 Table 159.Static characteristics: pin REF5V . . . . . . . . .127 Table 160.Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3 .128 Table 161 ...
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... NXP Semiconductors 26. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Fig 2. Pin configuration (LQFP128); top view . . . . . . . . .7 Fig 3. Internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Fig 4. SAF1761 clock scheme . . . . . . . . . . . . . . . . . . . .15 Fig 5. Memory segmentation and access block diagram .18 Fig 6. Adjusting analog overcurrent detection limit (optional .26 Fig 7. SAF1761 power supply connection . . . . . . . . . . .27 Fig 8. Most commonly used power supply connection .28 Fig 9 ...
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... NXP Semiconductors 27. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Host/peripheral roles Ordering information . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 14 7.1 SAF1761 internal architecture: advanced NXP slave host controller and hub . . . . . . . . . 14 7.1.1 Internal clock scheme and port selection . . . . 15 7 ...
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... NXP Semiconductors 9.5.1.2 Product ID register (R: 0372h 9.5.2 OTG Control register . . . . . . . . . . . . . . . . . . . 92 9.5.2.1 OTG Control register . . . . . . . . . . . . . . . . . . . 92 9.5.3 OTG Interrupt registers 9.5.3.1 OTG Status register . . . . . . . . . . . . . . . . . . . . 94 9.5.3.2 OTG Interrupt Latch register 9.5.3.3 OTG Interrupt Enable Fall register . . . . . . . . . 95 9.5.3.4 OTG Interrupt Enable Rise register . . . . . . . . 96 9.5.4 OTG Timer register . . . . . . . . . . . . . . . . . . . . . 97 9 ...
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... NXP Semiconductors 18.5 Errata added on 2009-04-20 150 18.5.1 Problem description . . . . . . . . . . . . . . . . . . . 150 18.5.2 Implication 151 18.5.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . 151 18.6 Errata added on 2009-04-20 151 18.6.1 Problem description . . . . . . . . . . . . . . . . . . . 151 18.6.2 Implication 152 18.6.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . 152 18.6.3.1 Condition 152 18.6.3.2 Condition 152 18.6.3.3 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 18 ...