SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 24

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
7.5 Phase-Locked Loop (PLL) clock multiplier
7.6 Power management
The OR function: If any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be
raised.
Table 5.
The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz
clock already existing in the system with a precision better than 50
use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI).
When an external crystal is used, make sure the CLKIN pin is connected to V
The PLL block generates all the main internal clocks required for normal functionality of
various blocks: 30 MHz, 48 MHz and 60 MHz.
No external components are required for the PLL operation.
The SAF1761 implements a flexible power management scheme, allowing various power
saving stages.
The usual powering scheme implies programming EHCI registers and the internal
Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed
USB host controller with a Hi-Speed USB hub attached.
When the SAF1761 is in suspend mode, the main internal clocks will be stopped to
ensure minimum power consumption. An internal LazyClock of 100 kHz
continue running. This allows initiating a resume on one of these events:
The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are bidirectional.
These pins must be connected to the GPIO pins of a processor.
The wake up state can be verified by reading the LOW level of this pin. If the level is HIGH,
it means that the SAF1761 is in the suspend state.
PTD
1
2
3
4
5
6
7
8
9
•
•
•
External USB device connect or disconnect
CS_N signal asserted when the SAF1761 is accessed
Driving the HC_SUSPEND/WAKEUP_N pin to a LOW logical level will wake up the
host controller, and driving the DC_SUSPEND/WAKEUP_N pin to a LOW logical level
will wake up the peripheral controller
AND register
1
1
0
1
0
0
0
0
0
Using the IRQ Mask AND or IRQ Mask OR registers
Rev. 01 — 18 November 2009
OR register
0
0
0
0
0
0
1
1
1
Time
1 ms
-
-
3 ms
-
-
5 ms
6 ms
7 ms
PTD done
1
1
-
1
-
-
1
1
1
Hi-Speed USB OTG controller
IRQ
-
-
-
active because of AND
-
-
active because of OR
active because of OR
active because of OR
10
SAF1761
© NXP B.V. 2009. All rights reserved.
6
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