SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 37

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 19.
[1]
Table 20.
[1]
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 14
13 to 0
The reserved bits should always be written with the reset value.
For details on register bit description, refer to
Symbol
-
FRINDEX[13:0] Frame Index: Bits in this register are used for the frame number in the SOF packet and as the
FRINDEX - Frame Index register (address: 002Ch) bit allocation
FRINDEX - Frame Index register (address: 002Ch) bit description
8.2.3 USBINTR register
8.2.4 FRINDEX register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
reserved
The USB Interrupt (USBINTR) register is a read or write register located at 0028h. All the
bits in this register are reserved.
The Frame Index (FRINDEX) register is used by the host controller to index into the
periodic frame list. The register updates every 125 s (once each microframe). Bits n to 3
are used to select a particular entry in the periodic frame list during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by the system software in the Frame List Size (FLS) field of the USBCMD register.
This register must be written as a double word. A word-only write (16-bit mode) produces
undefined results. A write to this register while the Run/Stop (R/S) bit is set produces
undefined results. Writes to this register also affect the SOF value. The bit allocation is
given in
Description
reserved
index into the frame list. The value in this register increments at the end of each time frame.
For example, microframe.
[1]
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Table
19.
[1]
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial Bus Rev.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 18 November 2009
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
FRINDEX[7:0]
reserved
reserved
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
FRINDEX[13:8]
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
R/W
R/W
R/W
R/W
37 of 166
24
16
0
0
8
0
0
0
1.0”.