SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 55

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 55.
[1]
Table 56.
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 11
10
9
8
The reserved bits should always be written with the reset value.
Symbol
-
OTG_IRQ_E
ISO_IRQ_E
ATL_IRQ_E
HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit allocation
HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit description
INT_IRQ_E
8.4.2 HcInterruptEnable register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
This register allows enabling or disabling of the IRQ generation because of various events
as described in
CLKREADY
Description
reserved; write reset value
OTG_IRQ Enable: Controls the IRQ assertion because of events present in the OTG Interrupt
Latch register.
0 — No IRQ will be asserted
1 — IRQ will be asserted
For details, see
ISO IRQ Enable: Controls the IRQ assertion when one or more ISO PTDs matching the ISO
IRQ Mask AND or ISO IRQ Mask OR register bits combination are completed.
0 — No IRQ will be asserted when ISO PTDs are completed
1 — IRQ will be asserted
For details, see
ATL IRQ Enable: Controls the IRQ assertion when one or more ATL PTDs matching the ATL
IRQ Mask AND or ATL IRQ Mask OR register bits combination are completed.
0 — No IRQ will be asserted when ATL PTDs are completed
1 — IRQ will be asserted
For details, see
R/W
R/W
R/W
R/W
30
22
14
0
0
0
_E
6
0
Table
reserved
HCSUSP_
Section
Section
Section
R/W
R/W
R/W
R/W
29
21
13
0
0
0
E
5
0
Rev. 01 — 18 November 2009
55.
[1]
7.4.
7.4.
7.4.
reserved
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
[1]
DMAEOT
INT _E
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
3
0
0
0
0
reserved
OTG_IRQ_
R/W
R/W
R/W
R/W
2
0
26
18
10
E
0
0
0
Hi-Speed USB OTG controller
[1]
ISO_IRQ_E
SOFITLINT
R/W
R/W
R/W
R/W
_E
25
17
0
0
9
0
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
reserved
ATL_IRQ
R/W
R/W
R/W
R/W
_E
55 of 166
24
16
0
0
8
0
0
0
[1]