SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 112

no-image

SAF1761BE/V1,557

Manufacturer Part Number
SAF1761BE/V1,557
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAF1761BE/V1,557

Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAF1761BE/V1,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 120. Endpoint MaxPacketSize register (address 0204h) bit description
Table 121. Endpoint Type register (address 0208h) bit allocation
[1]
SAF1761_1
Product data sheet
Bit
15 to 13
12 to 11
10 to 0
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
Symbol
-
NTRANS[1:0]
FFOSZ[10:0]
10.4.7 Endpoint Type register
R/W
R/W
15
0
0
7
0
0
The SAF1761 supports all the transfers given in
Rev.
Each programmable FIFO can be independently configured using its Endpoint
MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN
plus OUT), including set-up token buffer, control IN and control OUT, must not exceed
8192 bytes.
This register sets the endpoint type of the indexed endpoint: isochronous, bulk or
interrupt. It also serves to enable the endpoint and configure it for double buffering.
Automatic generation of an empty packet for a zero-length TX buffer can be disabled using
bit NOEMPKT. The register contains 2 bytes. See
reserved
Description
reserved
Number of Transactions: High-Speed (HS) mode only.
00 — One packet per microframe
01 — Two packets per microframe
10 — Three packets per microframe
11 — reserved
These bits are applicable only for isochronous or interrupt transactions.
FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint. Applies to both high-speed
and full-speed operations.
2.0”.
R/W
R/W
14
0
0
6
0
0
[1]
R/W
R/W
13
0
0
5
0
0
Rev. 01 — 18 November 2009
NOEMPKT
R/W
R/W
12
0
0
4
0
0
reserved
ENABLE
[1]
R/W
R/W
11
0
0
3
0
0
Ref. 1 “Universal Serial Bus Specification
Table
DBLBUF
121.
R/W
R/W
10
0
0
2
0
0
Hi-Speed USB OTG controller
R/W
R/W
9
0
0
1
ENDPTYP[1:0]
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
112 of 166
R/W
R/W
8
0
0
0
0
0

Related parts for SAF1761BE/V1,557