SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 111

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 117. DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit allocation
[1]
Table 118. DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit description
Table 119. Endpoint MaxPacketSize register (address 0204h) bit allocation
[1]
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
7 to 2
1 to 0
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
Symbol
-
BUF[1:0]
10.4.6 Endpoint MaxPacketSize register
R/W
R/W
R/W
15
7
0
0
0
0
7
0
0
Remark: For the endpoint IN data transfer, firmware must ensure a 200 ns delay between
writing of the data packet and reading the DcBufferStatus register. For the endpoint OUT
data transfer, firmware must also ensure a 200 ns delay between the reception of the
endpoint interrupt and reading the DcBufferStatus register.
This register determines the maximum packet size for all endpoints, except set-up buffer,
control IN and control OUT. The register contains 2 bytes, and the bit allocation is given in
Table
Each time the register is written, the Buffer Length register of the corresponding endpoint
is re-initialized to the FFOSZ field value. NTRANS bits control the number of transactions
allowed in a single microframe for high-speed isochronous and interrupt endpoints only.
reserved
Description
reserved
Buffer:
00 — The buffers are not filled.
01 — One of the buffers is filled.
10 — One of the buffers is filled.
11 — Both buffers are filled.
119.
R/W
R/W
R/W
14
6
0
0
0
0
6
0
0
[1]
R/W
R/W
R/W
13
5
0
0
0
0
5
0
0
Rev. 01 — 18 November 2009
reserved
[1]
R/W
R/W
R/W
12
4
0
0
0
0
4
0
0
NTRANS[1:0]
FFOSZ[7:0]
R/W
R/W
R/W
11
3
0
0
0
0
3
0
0
R/W
R/W
R/W
10
2
0
0
0
0
2
0
0
Hi-Speed USB OTG controller
FFOSZ[10:8]
BUF1
R/W
R/W
R
1
0
0
9
0
0
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
BUF0
111 of 166
R/W
R/W
R
0
0
0
8
0
0
0
0
0