SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 35

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 15.
[1]
Table 16.
[1]
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7
6 to 2
1
0
The reserved bits should always be written with the reset value.
For details on register bit description, refer to
Symbol
-
LHCR
-
HCRESET
RS
USBCMD - USB Command register (address 0020h) bit allocation
USBCMD - USB Command register (address 0020h) bit description
8.2.1 USBCMD register
LHCR
R/W
R/W
R/W
R/W
8.2 EHCI operational registers
31
23
15
0
0
0
7
0
The USB Command (USBCMD) register indicates the command to be executed by the
serial host controller. Writing to this register causes a command to be executed.
shows the USBCMD register bit allocation.
Description
reserved
Light Host Controller Reset (optional): If implemented, it allows the driver software to reset
the EHCI controller without affecting the state of the ports or the relationship to the companion
host controllers. If not implemented, a read of this field will always return logic 0.
reserved
Host Controller Reset: This control bit is used by the software to reset the host controller.
Run/Stop: 1 = Run. The host controller executes the schedule.
0 = Stop.
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
[1]
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial Bus Rev.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 18 November 2009
reserved
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
[1]
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
1
1
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
HCRESET
R/W
R/W
R/W
R/W
25
17
0
0
9
1
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
Table 15
R/W
R/W
R/W
R/W
RS
35 of 166
24
16
0
0
8
1
0
0
1.0”.