SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 46

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 40.
[1]
Table 41.
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7 to 4
3 to 2
1
0
The reserved bits should always be written with the reset value.
Symbol
DMA_COUNTER[23:0]
-
BURST_LEN[1:0]
ENABLE_DMA
DMA_READ_WRITE_SEL DMA Read/Write Select: Indicates if the DMA operation is a write or read to or
HcDMAConfiguration - Host Controller Direct Memory Access Configuration register (address 0330h) bit
allocation
HcDMAConfiguration - Host Controller Direct Memory Access Configuration register (address 0330h) bit
description
8.3.5 HcDMAConfiguration register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
The bit allocation of the HcDMAConfiguration register is given in
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
reserved
Description
DMA Counter: The number of bytes to be transferred (read or write).
Remark: Different number of bursts will be generated for the same transfer length
programmed in 16-bit and 32-bit modes because DMA_COUNTER is in number of
bytes.
reserved
DMA Burst Length:
00 — Single DMA burst
01 — 4-cycle DMA burst
10 — 8-cycle DMA burst
11 — 16-cycle DMA burst
Enable DMA:
0 — Terminate DMA
1 — Enable DMA
from the SAF1761.
0 — DMA write to the SAF1761 internal RAM is set
1 — DMA read from the SAF1761 internal RAM
[1]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 18 November 2009
DMA_COUNTER[23:16]
DMA_COUNTER[15:8]
DMA_COUNTER[7:0]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
R/W
R/W
R/W
R/W
BURST_LEN[1:0]
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
Table
ENABLE
_DMA
R/W
R/W
R/W
R/W
17
25
9
0
1
0
0
0
SAF1761
40.
© NXP B.V. 2009. All rights reserved.
DMA_READ_
WRITE_SEL
R/W
R/W
R/W
R/W
16
24
8
0
0
0
0
0
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