SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 97

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 94.
[1]
Table 95.
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30 to 24
23 to 0
The reserved bits should always be written with the reset value.
Symbol
START_TMR
-
TIMER_INIT_
VALUE[23:0]
OTG Timer register (address low word set: 0388h, low word clear: 038Ah; high word set: 038Ch, high
word clear: 038Eh) bit allocation
OTG Timer register (address low word set: 0388h, low word clear: 038Ah; high word set: 038Ch, high
word clear: 038Eh) bit description
9.5.4.1 OTG Timer register
START_
9.5.4 OTG Timer register
R/S/C
R/S/C
R/S/C
R/S/C
TMR
31
23
15
0
0
0
7
0
This is a 32-bit register organized as two 16-bit fields. These two fields have separate set
and clear addresses.
R/S/C
R/S/C
R/S/C
R/S/C
30
22
14
0
0
0
6
0
Description
This is the start/stop bit of the OTG timer. Writing logic 1 will cause the OTG timer to
load TMR_INIT_VALUE into the counter and start to count. Writing logic 0 will stop the
timer. This bit is automatically cleared when the OTG timer is timed out.
0 — stop the timer
1 — start the timer
reserved
These bits define the initial value used by the OTG timer. The timer interval is 0.01 ms.
Maximum time allowed is 167.772 s.
R/S/C
R/S/C
R/S/C
R/S/C
29
21
13
0
0
0
5
0
Rev. 01 — 18 November 2009
Table 94
TIMER_INIT_VALUE[23:16]
TIMER_INIT_VALUE[15:8]
TIMER_INIT_VALUE[7:0]
R/S/C
R/S/C
R/S/C
R/S/C
shows the bit allocation of the register.
28
20
12
0
0
0
4
0
reserved
R/S/C
R/S/C
R/S/C
R/S/C
27
19
11
0
0
0
3
0
[1]
R/S/C
R/S/C
R/S/C
R/S/C
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
R/S/C
R/S/C
R/S/C
R/S/C
25
17
0
0
9
0
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
R/S/C
R/S/C
R/S/C
R/S/C
97 of 166
24
16
0
0
8
0
0
0