SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 47

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 42.
[1]
Table 43.
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 3
2
1
0
The reserved bits should always be written with the reset value.
Symbol
-
ISO_BUF_FILL ISO Buffer Filled:
INT_BUF_FILL
ATL_BUF_FILL ATL Buffer Filled:
HcBufferStatus - Host Controller Buffer Status register (address 0334h) bit allocation
HcBufferStatus - Host Controller Buffer Status register (address 0334h) bit description
8.3.6 HcBufferStatus register
R/W
R/W
R/W
R/W
31
23
15
7
0
0
0
0
The HcBufferStatus register is used to indicate the HC that a particular PTD buffer (that is,
ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets
the Buffer Filled bit of a particular transfer in the HcBufferStatus register, the HC will start
traversing through PTD headers that are not marked for skipping and are valid PTDs.
Remark: Software can set these bits during the initialization.
Table 42
Description
reserved
1 — Indicates one of the ISO PTDs is filled, and the ISO PTD area will be processed.
0 — Indicates there is no PTD in this area. Therefore, processing of ISO PTDs will completely
be skipped.
INT Buffer Filled:
1 — Indicates one of the INT PTDs is filled, and the INT PTD area will be processed.
0 — Indicates there is no PTD in this area. Therefore, processing of INT PTDs will completely
be skipped.
1 — Indicates one of the ATL PTDs is filled, and the ATL PTD area will be processed.
0 — Indicates there is no PTD in this area. Therefore, processing of ATL PTDs will completely
be skipped.
R/W
R/W
R/W
R/W
30
22
14
6
0
0
0
0
shows the bit allocation of the HcBufferStatus register.
reserved
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 18 November 2009
[1]
R/W
R/W
R/W
R/W
28
20
12
4
0
0
0
0
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
0
3
27
19
11
0
0
0
ISO_BUF_
FILL
R/W
R/W
R/W
R/W
26
18
10
2
0
0
0
0
Hi-Speed USB OTG controller
INT_BUF_
FILL
R/W
R/W
R/W
R/W
25
17
1
0
0
0
9
0
SAF1761
© NXP B.V. 2009. All rights reserved.
ATL_BUF_
FILL
R/W
R/W
R/W
R/W
47 of 166
24
16
0
0
0
0
8
0